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ADSP-21375 - SHARC Processor

Description

3 SHARC Family Core Architecture 4 Family Peripheral Architecture 6 I/O Processor

Features

  • include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios Available in a 208-lead LQFP_EP package SIMD Core Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy FLAGx/IRQx/ TMREXP JTAG Block 0 RAM/ROM Internal Memory Block 1 RAM/ROM Block 2 RAM Block 3 RAM S DMD 64-BIT PMD 64-BIT Core Bus Cross Bar D.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SHARC Processor ADSP-21371/ADSP-21375 SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory, ADSP-21371—1M bits of on-chip SRAM and 4M bits of on-chip mask-programmable ROM On-chip memory, ADSP-21375—0.5M bits of on-chip SRAM and 2M bits of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21371/ADSP-21375 processors are available with a 200/266 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 56.
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