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ADRF6520 Datasheet

Dual Programmable Filters and VGAs

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Data Sheet
Dual Programmable Filters and VGAs for
2 GHz Channel Spacing for µW Radios
ADRF6520
FEATURES
Matched VGAs and programmable filters
Maximum gain: 53 dB
Continuous gain control range: 60 dB
Filter bypass mode I/Q bandwidth
±1 dB gain flatness: >1250 MHz
4-pole Butterworth filter I/Q bandwidth: 36 MHz to 720 MHz
RMS detector
IMD3: <−55 dBc for 1.5 V p-p composite output
HD2, HD3: <−55 dBc for 1.5 V p-p output
Noise figure: 10.5 dB at maximum gain
NF < 11 dB over 12 dB of VGA2 gain backoff
100 Ω differential input, low impedance output
Optional dc output offset correction
SPI-programmable filter corners
Single 3.3 V supply operation with power-down feature
APPLICATIONS
Point-to-point and point-to-multipoint radios
Baseband IQ receivers
Diversity receivers
ADC drivers
Instrumentation
Medical
GENERAL DESCRIPTION
The ADRF6520 is a matched pair of fully differential low noise and
low distortion programmable filters and variable gain amplifiers
(VGAs). Each channel is capable of rejecting large, out of band
interferers while reliably boosting the wanted signal, thus reducing
the bandwidth and resolution requirements on the analog-to-
digital converters (ADCs). The excellent matching between
channels and their high spurious-free dynamic range over all
gain and bandwidth settings make the ADRF6520 ideal for
quadrature-based (IQ) communication systems with dense
constellations, multiple carriers, and nearby interferers. The
filter corners, enable, and dc offset correction loop enable are
all programmable via a serial peripheral interface (SPI).
The first VGA that precedes the filters offers 30 dB of continuous
gain control with a maximum gain of 18 dB and sets a differential
input impedance of 100 Ω. The filters provide a four-pole
Butterworth response with −1 dB corner frequencies: 36 MHz,
72 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz.
For operation beyond 720 MHz, the filter can be disabled and
completely bypassed, thereby extending the −1 dB bandwidth
FUNCTIONAL BLOCK DIAGRAM
INP1 1
INM1 2
COM 3
CFLT1 4
CFLT2 5
COM 6
INM2 7
INP2 8
ADRF6520
DETECTOR
24 OPP1
23 OPM1
22 COM
21 VGN1
20 VGN2
19 COM
18 OPM2
17 OPP2
Figure 1
up to 1.25 GHz. A wideband rms detector is available to
monitor the signal at the filter inputs. A fixed gain amplifier of
6 dB immediately follows the filter. The postfilter VGA provides
30 dB of continuous gain control with a maximum gain of
12 dB. The output buffers offer an additional 18 dB of gain and
provide a differential output impedance of 20 Ω. The output
buffers are capable of driving 1.5 V p-p into 100 Ω loads at better
than 55 dBc nominal for the third-order intermodulation
distortion (IMD3). Independent, built in, dc offset correction
loops for each channel can be disabled via the SPI if fully dc-
coupled operation is desired. The high-pass corner frequency is
determined by external capacitors on the CHP1 and CHP2 pins
and the postfilter VGA gain.
The ADRF6520 operates from a 3.15 V to 3.45 V supply and
consumes a maximum supply current of 425 mA. When fully
disabled, it consumes ≤10 mA. The ADRF6520 is fabricated in
an advanced silicon-germanium BiCMOS process and is
available in a 32-lead, exposed pad LFCSP. Performance is
specified over the −40°C to +85°C temperature range.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

ADRF6520 Datasheet

Dual Programmable Filters and VGAs

No Preview Available !

ADRF6520
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 19
Input VGAs ................................................................................. 19
RMS Detector.............................................................................. 19
Programmable Filters................................................................. 20
Variable Gain Amplifiers........................................................... 20
Output Buffers/ADC Drivers ................................................... 20
DC Offset Compensation Loop................................................ 21
Programming the ADRF6520................................................... 21
Noise Characteristics ................................................................. 21
REVISION HISTORY
4/2017—Revision 0: Initial Version
Data Sheet
Distortion Characteristics ......................................................... 22
Maximizing the Dynamic Range ............................................. 22
Key Parameters for Quadrature-Based Receivers .................. 23
SPI Register and Timing................................................................ 24
Register Read/Write Timing ..................................................... 25
Applications Information .............................................................. 26
Basic Connections...................................................................... 26
Supply Decoupling ..................................................................... 26
Input Signal Path ........................................................................ 26
Output Signal Path ..................................................................... 26
DC Offset Compensation Loop Enabled ................................ 26
Serial Port Connections............................................................. 26
Enable/Disable Function ........................................................... 27
Gain Pin Decoupling ................................................................. 27
RMS Detector Connections ...................................................... 27
VGA2 Gain step response ......................................................... 27
Linear Operation of the ADRF6520 ........................................ 27
Evaluation Board ............................................................................ 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
Rev. 0 | Page 2 of 29


Part Number ADRF6520
Description Dual Programmable Filters and VGAs
Maker Analog Devices
Total Page 29 Pages
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