SPI Interface, 4 Ω RON, ±15 V/+12 V/±5 V,
1.8 V Logic Control, 8:1/Dual 4:1 Muxes
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 interface
Round robin mode allows switching times comparable with a
General-purpose digital outputs to control other devices,
such as parallel switches from Analog Devices, Inc.
4 Ω typical on resistance at 25°C
0.5 Ω typical on-resistance flatness at 25°C
0.2 Ω typical on-resistance match between channels at 25°C
VSS to VDD analog signal range
Fully specified at ±15 V, ±5 V, and +12 V
Power-up sequence of VDD, VSS, and GND before applying
VL and digital/analog inputs
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP package
Automated test equipment
Data acquisition systems
Audio signal routing
Video signal routing
The ADGS1408/ADGS1409 are analog multiplexers comprising
eight single channels and four differential channels, respectively.
A serial peripheral interface (SPI) controls the switches. The SPI
interface has robust error detection features such as cyclic
redundancy check (CRC) error detection, invalid read/write
address detection, and SCLK count error detection.
It is possible to daisy-chain multiple ADGS1408/ADGS1409
devices together. Daisy-chain mode enables the configuration of
multiple devices with a minimal amount of digital lines. The
ADGS1408/ADGS1409 can also operate in burst mode to
decrease the time between SPI commands.
iCMOS construction ensures ultra low power dissipation, making
the devices ideally suited for portable and battery-powered
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAMS
SCLK SDI CS RESET/VL
Figure 1. ADGS1408 Functional Block Diagram
SCLK SDI CS RESET/VL
Figure 2. ADGS1409 Functional Block Diagram
supplies. In the off condition, signal levels up to the supplies
The on-resistance profile is flat over the full analog input range,
which ensures linearity and low distortion when switching
1. SPI interface removes the need for parallel conversion,
logic traces, and reduces GPIO channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensure a robust digital
4. CRC and error detection capabilities allow the use of the
ADGS1408/ADGS1409 in safety critical systems.
5. Minimal distortion.
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