ADCLK846 - 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

Analog Devices

General Description

The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation.

Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs.

Key Features

Selectable LVDS/CMOS outputs Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs.

📥 Download Datasheet

ADCLK846 6 lvds/12 cmos outputs low power clock fanout buffer by Analog Devices - Datasheet Preview

Datasheet Details

Part number	ADCLK846
Manufacturer	Analog Devices
File Size	697.52 KB
Description	6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer
Datasheet	ADCLK846 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846 FUNCTIONAL BLOCK DIAGRAM ADCLK846 LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK CLK CTRL_A LVDS/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) CTRL_B SLEEP OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) 07226-001 FEATURES Selectable LVDS/CMOS outputs Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2.0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 65 ps output-to-output skew (LVDS) Sleep mode Pin-programmable control 1.