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Analog Devices Semiconductor Electronic Components Datasheet

AD9979 Datasheet

CCD Signal Processor

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14-Bit, CCD Signal Processor with
Precision Timing Core
AD9979
FEATURES
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with –3 dB, 0 dB, +3 dB, and
+6 dB gain
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
14-bit 65 MHz analog-to-digital converter
Black-level clamp with variable level control
Complete on-chip timing generator
Precision Timing™ core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and system
support
7 mm × 7 mm, 48-lead LFCSP
Internal LDO regulator circuitry
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
GENERAL DESCRIPTION
The AD9979 is a highly integrated CCD signal processor for
high speed digital video camera applications. Specified at pixel
rates of up to 65 MHz, the AD9979 consists of a complete
analog front end with analog-to-digital conversion, combined
with a programmable timing driver. The Precision Timing core
allows adjustment of high speed clocks with approximately
240 ps resolution at 65 MHz operation.
The analog front end includes black-level clamping, CDS, VGA,
and a 65 MSPS, 14-bit analog-to-digital converter (ADC). The
timing driver provides the high speed CCD clock drivers for RG,
HL, and H1 to H4. Operation is programmed using a 3-wire
serial interface.
Available in a space-saving, 7 mm × 7 mm, 48-lead LFCSP,
the AD9979 is specified over an operating temperature range of
−25°C to +85°C.
CCDINP
CCDINM
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9979
VREF
CDS
VGA
–3dB, 0dB, +3dB, +6dB
6dB TO 42dB
ADC
CLAMP
14 DOUT
D0 TO D13
LDOOUT
LDO
RG
HL
H1 TO H4
4 HORIZONTAL
DRIVERS
GPO1 GPO2
INTERNAL CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
HD VD
Figure 1.
INTERNAL
REGISTERS
SL SCK SDI
CLI
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.


Analog Devices Semiconductor Electronic Components Datasheet

AD9979 Datasheet

CCD Signal Processor

No Preview Available !

AD9979
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Digital Specifications ................................................................... 5
Analog Specifications................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Equivalent Input/Output Circuits ................................................ 11
Theory of Operation ...................................................................... 12
Programmable Timing Generation.............................................. 13
Precision Timing High Speed Timing Core............................. 13
Horizontal Clamping and Blanking......................................... 16
REVISION HISTORY
10/09—Rev. B to Rev. C
Changes to Clock Rate (CLI) Parameter, Table 1 ......................... 3
9/09—Rev. A to Rev. B
Changed SCK Falling Edge to SDATA Valid Hold Parameter to
SCK Rising Edge to SDATA Hold .................................................. 4
Changes to Individual HBLK Patterns Section .......................... 18
6/09—Rev. Sp0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Figure 2.......................................................................... 6
Changes to Table 5 and Thermal Resistance Section................... 7
Complete Field—Combining H-Patterns ............................... 23
Mode Registers ........................................................................... 24
Horizontal Timing Sequence Example.................................... 26
General-Purpose Outputs (GPO) ............................................ 27
GP Look-Up Tables (LUT)........................................................ 30
Analog Front-End Description and Operation...................... 31
Applications Information .............................................................. 35
Recommended Power-Up Sequence ....................................... 35
Standby Mode Operation .......................................................... 37
CLI Frequency Change.............................................................. 37
Circuit Configuration ................................................................ 38
Grounding and Decoupling Recommendations.................... 38
3-Wire Serial Interface Timing..................................................... 40
Layout of Internal Registers ...................................................... 41
Updating of New Register Values............................................. 42
Complete Register Listing ......................................................... 43
Outline Dimensions ....................................................................... 54
Ordering Guide .......................................................................... 54
Changes to Figure 3 and Table 7......................................................8
Changes to Figure 22...................................................................... 16
Added GP_LINE_MODE Name, Table 16 ................................. 28
Changes to Figure 42...................................................................... 31
Added Example Register Settings for Power-Up Section.......... 36
Changes to Additional Restriction Section................................. 37
Changes to Table 22, 3 V System Compatibility Section, and
Grounding and Decoupling Recommendations Section .......... 38
Changes to Table 33 ....................................................................... 51
Changes to Table 34 ....................................................................... 52
Added Exposed Paddle Notation to Outline Dimensions ........ 54
2/07—Revision Sp0: Initial Version
Rev. C | Page 2 of 56


Part Number AD9979
Description CCD Signal Processor
Maker Analog Devices
Total Page 30 Pages
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