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Analog Devices Semiconductor Electronic Components Datasheet

AD9695 Datasheet

Dual Analog-to-Digital Converter

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Data Sheet
14-Bit, 1300 MSPS/625 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9695
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 16 Gbps
1.6 W total power at 1300 MSPS
800 mW per ADC channel
SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)
SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)
Noise density
−153.9 dBFS/Hz (1.59 V p-p input range)
−155.6 dBFS/Hz (2.04 V p-p input range)
0.95 V, 1.8 V, and 2.5 V supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)
2 GHz usable analog input full power bandwidth
>95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated digital downconverters per ADC channel
48-bit NCO
Programmable decimation rates
Differential clock input
SPI control
Integer clock divide by 2 and divide by 4
Flexible JESD204B lane configurations
On-chip dithering to improve small signal linerarity
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, WCDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation
Oscilloscopes
Spectrum analyzers
Network analyzers
Integrated RF test solutions
Radars
Electronic support measures, electronic counter measures,
and electronic counter-counter measures
High speed data acquisition systems
DOCSIS 3.0 CMTS upstream receive paths
Hybrid fiber coaxial digital reverse path receivers
Wideband digital predistortion
AVDD1
(0.95V)
AVDD2
(1.8V)
FUNCTIONAL BLOCK DIAGRAM
AVDD3 AVDD1_SR
(2.5V) (0.95V)
DVDD DRVDD1 DRVDD2 SPIVDD
(0.95V) (0.95V) (1.8V)
(1.8V)
VIN+A
VIN–A
VIN+B
VIN–B
VREF
PDWN/STBY
SYSREF±
CLK+
CLK–
BUFFER
ADC
CORE
14
FAST
DETECT
SIGNAL
MONITOR
BUFFER
ADC
CORE
14
JESD204B
SUBCLASS 1
CONTROL
CLOCK
DISTRIBUTION
÷2
÷4
DIGITAL DOWN-
CONVERTER
DIGITAL DOWN-
CONVERTER
SPI AND
CONTROL
REGISTERS
JESD204B
LINK
AND
Tx
OUTPUTS
4
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
GPIO MUX
AD9695
FD_A/GPIO_A0
FD_B/GPIO_B0
AGND
SDIO SCLK CSB
Figure 1.
DRGND DGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

AD9695 Datasheet

Dual Analog-to-Digital Converter

No Preview Available !

AD9695
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ........................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications—1300 MSPS.................................................. 6
AC Specifications—625 MSPS.................................................... 8
Digital Specifications ................................................................... 9
Switching Specifications ............................................................ 10
Timing Specifications ................................................................ 11
Absolute Maximum Ratings.......................................................... 13
Thermal Characteristics ............................................................ 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 16
1300 MSPS................................................................................... 16
625 MSPS..................................................................................... 21
Equivalent Circuits ......................................................................... 25
Theory of Operation ...................................................................... 27
ADC Architecture ...................................................................... 27
Analog Input Considerations.................................................... 27
Voltage Reference ....................................................................... 30
DC Offset Calibration................................................................ 30
Clock Input Considerations ...................................................... 30
Power-Down/Standby Mode..................................................... 33
Temperature Diode .................................................................... 33
ADC Overrange and Fast Detect.................................................. 34
ADC Overrange.......................................................................... 34
Fast Threshold Detection (FD_A and FD_B) ........................ 34
ADC Application Modes and JESD204B Tx Converter Mapping
........................................................................................................... 35
Programmable Finite Impulse Response (FIR) Filters .............. 37
Supported Modes........................................................................ 37
Programming Instructions........................................................ 39
Digital Downconverter (DDC)..................................................... 42
DDC I/Q Input Selection .......................................................... 42
DDC I/Q Output Selection ....................................................... 42
DDC General Description ........................................................ 42
DDC Frequency Translation..................................................... 45
DDC Decimation Filters ........................................................... 53
DDC Gain Stage ......................................................................... 60
DDC Complex to Real Conversion ......................................... 61
DDC Mixed Decimation Settings ............................................ 62
DDC Example Configurations ................................................. 64
Signal Monitor ................................................................................ 67
SPORT Over JESD204B ............................................................ 68
Digital Outputs ............................................................................... 70
Introduction to the JESD204B Interface ................................. 70
JESD204B Overview .................................................................. 70
Functional Overview ................................................................. 71
JESD204B Link Establishment ................................................. 71
Physical Layer (Driver) Outputs .............................................. 73
Setting Up the AD9695 Digital Interface ................................ 74
Deterministic Latency.................................................................... 80
Subclass 0 Operation.................................................................. 80
Subclass 1 Operation.................................................................. 80
Multichip Synchronization............................................................ 82
Normal Mode.............................................................................. 82
Timestamp Mode ....................................................................... 82
SYSREF± Input ........................................................................... 84
SYSREF± Setup/Hold Window Monitor................................. 86
Latency............................................................................................. 88
End to End Total Latency.......................................................... 88
Example Latency Calculations.................................................. 88
LMFC Referenced Latency........................................................ 88
Test Modes....................................................................................... 90
ADC Test Modes ........................................................................ 90
JESD204B Block Test Modes .................................................... 91
Serial Port Interface (SPI).............................................................. 93
Configuration Using the SPI..................................................... 93
Hardware Interface..................................................................... 93
SPI Accessible Features.............................................................. 93
Memory Map .................................................................................. 94
Reading the Memory Map Register Table............................... 94
Memory Map Registers ............................................................. 95
Applications Information ............................................................ 133
Power Supply Recommendations........................................... 133
Rev. A | Page 2 of 135


Part Number AD9695
Description Dual Analog-to-Digital Converter
Maker Analog Devices
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AD9695 Datasheet PDF






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