Fully integrated VCO/PLL core 0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz 0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.40 ps rms jitter from 12 .

GbE/FC/SONET line cards, switches, and routers CPU/PCI-E applications Low jitter, low phase noise clock generation GENE.

The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, l.

AD9571

AD9572

AD9573

AD9574

AD9576

AD9577

AD9578

AD9500

AD9501

AD9502

AD9508

AD9510

AD9511

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