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AD9575 - Network Clock Generator

Description

The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking.

Features

  • Fully integrated VCO/PLL core 0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz 0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz 0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz Input crystal frequency of 19.44 MHz, 25 MHz, or 25.78125 MHz Pin selectable divide ratios for 33.33 MHz, 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 161.13 MHz, and 312.5 MHz outputs LVDS/LVPECL/LVCMOS output for.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Network Clock Generator, Two Outputs AD9575 FEATURES Fully integrated VCO/PLL core 0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz 0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz 0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz Input crystal frequency of 19.44 MHz, 25 MHz, or 25.78125 MHz Pin selectable divide ratios for 33.33 MHz, 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 161.13 MHz, and 312.5 MHz outputs LVDS/LVPECL/LVCMOS output format Integrated loop filter Space saving 4.4 mm × 5.0 mm TSSOP 100 mA power supply current (LVDS output) 120 mA power supply current (LVPECL output) 3.
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