Datasheet4U Logo Datasheet4U.com

AD9547 - Dual/Quad Input Network Clock Generator/Synchronizer

Description

The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH).

The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references.

Features

  • Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 kHz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input refe.

📥 Download Datasheet

Datasheet Details

Part number AD9547
Manufacturer Analog Devices
File Size 1.55 MB
Description Dual/Quad Input Network Clock Generator/Synchronizer
Datasheet download datasheet AD9547 Datasheet

📁 Similar Datasheet

  • AD9256 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD9256H - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD92580 - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD92580C - DIGITAL AMPLIFIER POWER STAGE (Elite Semiconductor)
  • AD9700 - Video Dispaly D/A Converter (ETC)
Other Datasheets by Analog Devices
  • AD9540 - 655 MHz Low Jitter Clock Generator
  • AD9543 - Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
  • AD9545 - 1 pps Synchronizer and Jitter Cleaner
  • AD9548 - Quad/Octal Input Network Clock Generator/Synchronizer
  • AD9549 - Dual Input Network Clock Generator/Synchronizer
  • AD9500 - Digitally Programmable Delay Generator
  • AD9501 - Digitally Programmable Delay Generator
  • AD9502 - Hybrid RS-170 Video Digitizer

Full PDF Text Transcription

Click to expand full text
Data Sheet Dual/Quad Input Network Clock Generator/Synchronizer AD9547 FEATURES Supports Stratum 2 stability in holdover mode Supports reference switchover with phase build-out Supports hitless reference switchover Automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair configurable as a single differential input or as 2 independent singleended inputs Input reference frequencies from 1 kHz to 750 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 30-bit programmable input reference divider 2 pairs of clock output pins, with each pair configurable as a single differential LVDS/LVPECL output or as 2 singleended CMOS outputs Output frequencies up to 450 MHz 20-bit integer and 10-bit fractional
Published: |