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AD9525 - Low Jitter Clock Generator

General Description

The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs.

Key Features

  • Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input.

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Other Datasheets by Analog Devices

Part Number Description
AD9520-0 12 LVPECL/24 CMOS Output Clock Generator
AD9520-1 12 LVPECL/24 CMOS Output Clock Generator
AD9520-2 12 LVPECL/24 CMOS Output Clock Generator
AD9520-3 12 LVPECL/24 CMOS Output Clock Generator
AD9520-4 12 LVPECL/24 CMOS Output Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data Sheet FEATURES Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input APPLICATIONS LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100 Gb/sec OTN line side clocking Cable/DOCSIS CMTS clocking Test and measurement GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO.