AD9267 Datasheet | Analog Devices

FEATURES SNR: 83 d B (85 d BFS) to 10 MHz input SFDR: - 88 d Bc to 10 MHz input Noise figure: 15 d B Input impedance: 1 kΩ Power: 416 m W 10 MHz real or 20 MHz plex bandwidth 1.8 V analog supply operation On-chip PLL clock multiplier On-chip voltage reference Twos plement data format 640 MSPS, 4-bit LVDS data output Serial control interface (SPI) FUNCTIONAL BLOCK DIAGRAM AVDD PDWNB PDWNA DRVDD OR±A VIN+A VIN- A LVDS DRIVERS Σ -Δ MODULATOR D3±A D0±A PLL_LOCKED PLLMULT4 PLLMULT3 PLLMULT2 CLK+ CLK- DCO± VREF CFILT VIN- B VIN+B Σ -Δ MODULATOR PHASELOCKED LOOP LVDS DRIVERS D3±B D0±B OR±B 07773-001 APPLICATIONS Baseband quadrature receivers: CDMA2000, W-CDMA, multicarrier GSM/EDGE, 802.16x, and LTE Quadrature sampling instrumentation SERIAL INTERFACE AGND SDIO/ PLLMULT1 SCLK/ PLLMULT0 DGND GENERAL DESCRIPTION The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ) modulator with - 88 d Bc of dynamic range over 10 MHz real or 20 MHz plex bandwidth. The bination of high dynamic range, wide bandwidth, and characteristics unique to the continuous time Σ-Δ modulator architecture makes the AD9267 an ideal solution for wireless munication systems. The AD9267 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled fifth-order continuous time loop filter attenuates out-of-band signals and aliases, reducing the need for external filters at the input. The low noise figure of 15 d B relaxes the linearity requirements of the front-end signal chain ponents, and the high dynamic range reduces the need for an automatic gain control (AGC) loop. A differential input clock controls all internal conversion cycles. An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. The digital output data is presented as 4-bit, LVDS at 640 MSPS in twos plement format. A data clock output (DCO) is provided to ensure...