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Analog Devices Semiconductor Electronic Components Datasheet

AD9201 Datasheet

Dual Channel/ 20 MHz 10-Bit Resolution CMOS ADC

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a
FEATURES
Complete Dual Matching ADCs
Low Power Dissipation: 215 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.4 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 57.8 dB
Over Nine Effective Bits
Spurious-Free Dynamic Range: –73 dB
No Missing Codes Guaranteed
28-Lead SSOP
Dual Channel, 20 MHz 10-Bit
Resolution CMOS ADC
AD9201
IINA
IINB
IREFB
IREFT
QREFB
QREFT
VREF
REFSENSE
QINB
QINA
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CLOCK
DVDD DVSS
"I" ADC
I
REGISTER
AD9201
REFERENCE
BUFFER
ASYNCHRONOUS
MULTIPLEXER
1V
THREE-
STATE
OUTPUT
BUFFER
"Q" ADC
Q
REGISTER
SLEEP
SELECT
DATA
10 BITS
CHIP
SELECT
PRODUCT DESCRIPTION
The AD9201 is a complete dual channel, 20 MSPS, 10-bit
CMOS ADC. The AD9201 is optimized specifically for applica-
tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 20 MHz
sampling rate and wide input bandwidth will cover both narrow-
band and spread-spectrum channels. The AD9201 integrates two
10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.
Each ADC incorporates a simultaneous sampling sample-and-
hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica-
tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi-
plexed digital output buffer.
The AD9201 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 215 mW of power (on 3 V supply). The AD9201 input
structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
its 10 MHz Nyquist input frequencies.
PRODUCT HIGHLIGHTS
1. Dual 10-Bit, 20 MSPS ADCs
A pair of high performance 20 MSPS ADCs that are opti-
mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.
2. Low Power
Complete CMOS Dual ADC function consumes a low
215 mW on a single supply (on 3 V supply). The AD9201
operates on supply voltages from 2.7 V to 5.5 V.
3. On-Chip Voltage Reference
The AD9201 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.
4. On-chip analog input buffers eliminate the need for external
op amps in most applications.
5. Single 10-Bit Digital Output Bus
The AD9201 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.
6. Small Package
The AD9201 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9201 dual ADC is pin compatible with a dual 8-bit
ADC (AD9281) and has a companion dual DAC product,
the AD9761 dual DAC.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999


Analog Devices Semiconductor Electronic Components Datasheet

AD9201 Datasheet

Dual Channel/ 20 MHz 10-Bit Resolution CMOS ADC

No Preview Available !

AD9201–SPECIFICATIONS (AVDD = +3 V, DVDD = +3 V, FSAMPLE = 20 MSPS, VREF = 2 V, INB = 0.5 V, TMIN to TMAX,
internal ref, differential input signal, unless otherwise noted)
Parameter
Symbol Min Typ Max
Units Condition
RESOLUTION
10 Bits
CONVERSION RATE
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Differential Nonlinearity (SE)
Integral Nonlinearity (SE)
Zero-Scale Error, Offset Error
Full-Scale Error, Gain Error
Gain Match
Offset Match
FS
DNL
INL
DNL
INL
EZS
EFS
20
± 0.4
1.2
± 0.5 ± 1
± 1.5 ± 2.5
± 1.5 ± 3.8
± 3.5 ± 5.4
± 0.5
±5
MHz
LSB
LSB
LSB
LSB
% FS
% FS
LSB
LSB
REFT = 1 V, REFB = 0 V
REFT = 1 V, REFB = 0 V
ANALOG INPUT
Input Voltage Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Aperture Delay Match
Input Bandwidth (–3 dB)
Small Signal (–20 dB)
Full Power (0 dB)
AIN –0.5
AVDD/2 V
CIN 2
tAP 4
tAJ 2
2
pF
ns
ps
ps
BW
240 MHz
245 MHz
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
Output Voltage Tolerance (2 V Mode)
Load Regulation (1 V Mode)
Load Regulation (2 V Mode)
VREF
VREF
1
± 10
2
± 15
± 28
± 15
V REFSENSE = VREF
mV
V REFSENSE = GND
mV
mV 1 mA Load Current
mV 1 mA Load Current
POWER SUPPLY
Operating Voltage
Supply Current
Power Consumption
Power-Down
Power Supply Rejection
DYNAMIC PERFORMANCE1
Signal-to-Noise and Distortion
f = 3.58 MHz
f = 10 MHz
Signal-to-Noise
f = 3.58 MHz
f = 10 MHz
Total Harmonic Distortion
f = 3.58 MHz
f = 10 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
f = 10 MHz
Two-Tone Intermodulation Distortion2
Differential Phase
Differential Gain
Crosstalk Rejection
AVDD
DRVDD
IAVDD
IDRVDD
PD
PSR
SINAD
SNR
THD
SFDR
IMD
DP
DG
2.7
2.7
55.6
55.9
–66
3 5.5
3 5.5
71.6
0.1
215 245
15.5
0.8 1.3
57.3
55.8
57.8
56.2
–69 –63.3
–66.3
–73
–70.5
–62
0.1
0.05
68
V
V
mA
mA
mW
mW
% FS
AVDD – DVDD 2.3 V
AVDD = 3 V
AVDD = DVDD = 3 V
STBY = AVDD, Clock = AVSS
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degree
%
dB
f = 44.49 MHz and 45.52 MHz
NTSC 40 IRE Mod Ramp
FS = 14.3 MHz
–2– REV. D


Part Number AD9201
Description Dual Channel/ 20 MHz 10-Bit Resolution CMOS ADC
Maker Analog Devices
Total Page 20 Pages
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