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Data Sheet
Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter AD9152
FEATURES
Supports input data rates up to 1.125 GSPS Proprietary low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF
SFDR = 72 dBc at 150 MHz IF, −6 dBFS Flexible 4-lane JESD204B interface Multiple chip synchronization
Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, and 8× interpolation filter Low power architecture Input signal power detection Emergency stop for downstream analog circuitry protection Transmit enable function allows extra power saving High performance, low noise, phase-locked loop (PLL) clock multiplier Digital inverse sinc filter and programmable finite impulse response (FIR) filter Low power: 1223 mW at 1.
AD9152 Datasheet
