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Analog Devices Semiconductor Electronic Components Datasheet

AD8802 Datasheet

12 Channel/ 8-Bit TrimDACs with Power Shutdown

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AD8802 pdf
a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D11
D10
D9
D8
D7
SER
REG
EN
ADDR
DEC
D D0
8
D7
DAC
REG
#1
D0
R
D7
DAC
REG
#12
D0
R
DAC
1
DAC
12
GND
RS VREFL
(AD8802 ONLY) (AD8804 ONLY)
VDD
VREFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


Analog Devices Semiconductor Electronic Components Datasheet

AD8802 Datasheet

12 Channel/ 8-Bit TrimDACs with Power Shutdown

No Preview Available !

AD8802 pdf
AD8802/AD8804–SPECIFICATIONS (VDD = +3 V ؎ 10% or +5 V ؎ 10%, VREFH = +VDD, VREFL = 0 V, –40؇C
TA +85؇C unless otherwise noted)
Parameter
Symbol Conditions
Min Typ1 Max Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Full-Scale Error
Zero Code Error
DAC Output Resistance
Output Resistance Match
REFERENCE INPUT
Voltage Range2
REFH Input Resistance
REFL Input Resistance3
Reference Input Capacitance3
DIGITAL INPUTS
Logic High
Logic Low
Logic High
Logic Low
Input Current
Input Capacitance3
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
Power Dissipation
Power Supply Sensitivity
DYNAMIC PERFORMANCE3
VOUT Settling Time
Crosstalk
N
DNL
INL
GFSE
VZSE
ROUT
R/RO
Guaranteed Monotonic
8
–1 ± 1/4
–1.5 ± 1/2
–1 1/2
–1 1/4
35
1.5
+1
+1.5
+1
+1
8
Bits
LSB
LSB
LSB
LSB
k
%
VREFH
VREFL
RREFH
RREFL
CREF0
CREF1
Pin Available on AD8804 Only
Digital Inputs = 55H, VREFH = VDD
Digital Inputs = 55H, VREFL = VDD
Digital Inputs all Zeros
Digital Inputs all Ones
0
VDD
V
0
VDD
V
1.2 k
1.2 k
32 pF
32 pF
VIH VDD = +5 V
VIL VDD = +5 V
VIH VDD = +3 V
VIL VDD = +3 V
IIL VIN = 0 V or + 5 V
CIL
2.4
2.1
5
V
0.8 V
V
0.6 V
± 1 µA
pF
VDD Range
IDD
IDD
IREFH
PDISS
PSRR
VIH = VDD or VIL = 0 V
VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V
SHDN = 0
VIH = VDD or VIL = 0 V, VDD = +5.5 V
VDD = +5 V ± 10%
2.7
0.01
1
0.2
0.001
5.5
10
4
10
55
0.002
V
µA
mA
µA
µW
%/%
tS ± 1/2 LSB Error Band
CT Between Adjacent Outputs5
0.6 µs
50 dB
SWITCHING CHARACTERISTICS3, 6
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCH, tCL
tDS
tDH
tCSS
tCSW
tRS
tCSH
tCS1
Clock Level High or Low
15
5
5
10
10
90
20
10
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1Typicals represent average readings at +25°C.
2VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD.
3Guaranteed by design and not subject to production test.
4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).
5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).
6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
–2– REV. 0


Part Number AD8802
Description 12 Channel/ 8-Bit TrimDACs with Power Shutdown
Maker Analog Devices
Total Page 16 Pages
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