16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
FUNCTIONAL BLOCK DIAGRAM
R/W RS VDD1 LD VDD2
16 x 8
16 x 8
DGND2 DACGND VEE
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
VDD2 LD•EN VREF
DGND2 RS DACGND
Figure 1. Equivalent DAC Channel
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