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Analog Devices Semiconductor Electronic Components Datasheet

AD8600 Datasheet

16-Channel/ 8-Bit Multiplying DAC

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AD8600 pdf
a
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
16-Channel, 8-Bit
Multiplying DAC
AD8600*
FUNCTIONAL BLOCK DIAGRAM
CS
EN
A3
A2
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W RS VDD1 LD VDD2
CONTROL
LOGIC
VREF VCC
ADDRESS
DECODE
16 x 8
INPUT
REGISTERS
16 x 8
DAC
REGISTERS
AD8600
16
8-BIT
DACS
DGND1
DGND2 DACGND VEE
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
± 1 LSB in 2 µs.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
*Patent pending.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
R/WCS•ADDR•EN VDD1
VDD2 LDEN VREF
VCC
DB7...DB0
INPUT
REGISTER
DAC
REGISTER
R-2R
DAC
OX
RS
DGND2 RS DACGND
VEE
DGND1
R/WCS•ADDRESS
Figure 1. Equivalent DAC Channel
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


Analog Devices Semiconductor Electronic Components Datasheet

AD8600 Datasheet

16-Channel/ 8-Bit Multiplying DAC

No Preview Available !

AD8600 pdf
AD8600–SPECIFICATIONS
SINGLE SUPPLY (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = 0 V, VREF = +2.500 V, –40°C TA +85°C, unless otherwise noted)
Parameter
Symbol Condition
Min Typ Max Units
STATIC PERFORMANCE1
Resolution
Relative Accuracy2
Differential Nonlinearity2
Full-Scale Voltage
Full-Scale Tempco
Zero Scale Error
Reference Input Resistance
N
INL
DNL
VFS
TCVFS
VZSE
VZSE
RREF
ANALOG OUTPUT
Output Voltage Range2
Output Current
Capacitive Load
OVRSS
IOUT
CL
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Logic Input Current
Logic Input Capacitance3
VIL
VIH
IIL
CIL
LOGIC OUTPUTS
Logic Out High Voltage
Logic Out Low Voltage
VOH
VOL
AC CHARACTERISTICS3
Slew Rate
Voltage Output Settling Time2
Voltage Output Settling Time2
SR
tS1
tS2
Guaranteed Monotonic
Data = FFH
Data = FFH
Data = 00H, RS = “0,” TA = +25°C
Data = 00H, RS = “0”
Data = ABH
VREF = +2.5 V
Data = 80H
No Oscillation
IOH = –0.4 mA
IOL = 1.6 mA
For VREF or FS Code Change
± 1 LSB of Final Value, Full-Scale Data Change
± 1 LSB of Final Value, VREF = 1 V, Data = FFH
8
–1
–1
2.480
1.2
± 1/2 +1
± 1/4 +1
2.490 2.500
± 20
+3.5
+5
2
Bits
LSB
LSB
V
ppm/°C
LSB
LSB
k
0.000
±2
50
2.500 V
mA
pF
0.8 V
2.4 V
10 µA
10 pF
3.5 V
0.4 V
47
2
2
V/µs
µs
µs
POWER SUPPLIES
Positive Supply Current
Logic Supply Currents
Power Dissipation
Power Supply Sensitivity
Logic Power Supply Range
Positive Power Supply Range3
ICC
IDD1&2
PDISS
PSS
VDDR
VCCR
VIH = 5 V, VIL = 0 V, No Load
VIH = 5 V, VIL = 0 V, No Load
VIH = 5 V, VIL = 0 V, No Load
VCC = ± 5%
24 35
mA
0.1 mA
120 175 mW
0.007 %/%
4.75 5.25 V
VDD 7.0 V
NOTES
1When VREF = 2.500 V, 1 LSB = 9.76 mV.
2Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V EE) pin of at least –0.7 V to
–5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7 10 to 8010.
3Guaranteed by design not subject to production test.
Specifications subject to change without notice.
–2– REV. 0


Part Number AD8600
Description 16-Channel/ 8-Bit Multiplying DAC
Maker Analog Devices
Total Page 16 Pages
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