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Analog Devices Semiconductor Electronic Components Datasheet

AD8582 Datasheet

+5 Volt/ Parallel Input Complete Dual 12-Bit DAC

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AD8582 pdf
a
FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, ±5 mA Drive
Very Low Power: 5 mW
APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals
GENERAL DESCRIPTION
The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (VREF) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.
The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ± 5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
5.0
∆∆VFS 1 LSB
DATA = FFFH
4.8 TA = +25°C
4.6
PROPER OPERATION
WHEN VDD SUPPLY
4.4 VOLTAGE ABOVE
CURVE
4.2
4.0
0.01
0.1 1.0 10
OUTPUT LOAD CURRENT – mA
100
Figure 1. Minimum Supply Voltage vs. Load
+5 Volt, Parallel Input
Complete Dual 12-Bit DAC
AD8582
FUNCTIONAL BLOCK DIAGRAM
AD8582
12
LDA
DAC A
REGISTER
12-BIT
DAC A
VDD
VOUTA
CS
A/B
DATA
LDB
INPUT A
REGISTER
12 2
INPUT B
REGISTER
REFERENCE
DAC B
REGISTER
12
12-BIT
DAC B
DGND
RST MSB
VREF
VOUTB
AGND
The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select CS input is strobed. An asynchro-
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
The AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
VDD = +5V
TA = –55°C, +25°C, +85°C
= +25°C & +85°C
= –55°C
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
Figure 2. Linearity Error vs. Digital Code and Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


Analog Devices Semiconductor Electronic Components Datasheet

AD8582 Datasheet

+5 Volt/ Parallel Input Complete Dual 12-Bit DAC

No Preview Available !

AD8582 pdf
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 V ± 5%, RL = No Load, –40°C TA +85°C, unless otherwise noted)
Parameter
Symbol Condition
Min
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Full-Scale Tempco
MATCHING PERFORMANCE
Linearity Matching Error
REFERENCE OUTPUT
Output Voltage
Output Source Current
Line Rejection
Load Regulation
ANALOG OUTPUT
Output Current
Load Regulation at Half Scale
Capacitive Load
DYNAMIC CHARACTERISTICS3
Crosstalk
Voltage Output Settling Time5
Digital Feedthrough
N
INL
DNL
VZSE
VFS
TCVFS
VFSA/B
VREF
IREF
LNREJ
LDREG
IOUT
LDREG
CL
CT
tS
FT
Note 1
Monotonic
Data = 000H
Data = FFFH,2
Notes 2 and 3
12
–2
–1
4.079
Note 4
IREF = 0 mA to 5 mA
Data = 800H
RL = 402 to , Data = 800H
No Oscillation3
2.484
To ± 1 LSB of Final Value
Signal Measured at DAC Output, While
Changing Data (LDA = LDB = “1”)
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
VIL
VIH
IIL
CIL Note 3
2.4
TIMING SPECIFICATIONS3, 6
Chip Select Pulse Width
DAC Select Setup
DAC Select Hold
Data Setup
Data Hold
Load Setup
Load Hold
Load Pulse Width
Reset Pulse Width
tCSW
tAS
tAH
tDS
tDH
tLS
tLH
tLDW
tRSW
30
30
0
30
10
20
10
20
30
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation7
Power Supply Sensitivity
IDD
PDISS
PSS
VIH = 2.4 V, VIL = 0.8 V
VIL = 0 V, VDD = +5 V
VIH = 2.4 V, VIL = 0.8 V
VIL = 0 V, VDD = +5 V
VDD = ± 5%
NOTES
11 LSB = 1 mV for 0 V to +4.095 V output range.
2Includes internal voltage reference error.
3These parameters are guaranteed by design and not subject to production testing.
4Very little sink current is available at the VREF pin. Use external buffer if setting up a virtual ground.
5Settling time is not guaranteed for the first six codes 0 through 5.
6All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7Power dissipation is a calculated value IDD × 5 V.
Specifications subject to change without notice.
Typ
± 3/4
± 3/4
+0.2
4.095
± 16
±1
2.500
1
500
>64
16
35
4
1
20
5
0.002
Max Units
+2
+1
+3
4.111
Bits
LSB
LSB
mV
V
ppm/°C
LSB
2.516
–5
0.08
0.1
V
mA
%/V
%/mA
± 5 mA
3 LSB
pF
dB
µs
nV s
0.8 V
V
10 µA
10 pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
2
35
10
0.004
mA
mA
mW
mW
%/%
–2– REV. 0


Part Number AD8582
Description +5 Volt/ Parallel Input Complete Dual 12-Bit DAC
Maker Analog Devices
Total Page 8 Pages
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