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Analog Devices Semiconductor Electronic Components Datasheet

AD7528 Datasheet

CMOS Dual 8-Bit Buffered Multiplying DAC

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a
FEATURES
On-Chip Latches for Both DACs
+5 V to +15 V Operation
DACs Matched to 1%
Four Quadrant Multiplication
TTL/CMOS Compatible
Latch Free (Protection Schottkys not Required)
APPLICATIONS
Digital Control of:
Gain/Attenuation
Filter Parameters
Stereo Audio Circuits
X-Y Graphics
CMOS Dual 8-Bit
Buffered Multiplying DAC
AD7528
VDD
DB0
DATA
INPUTS
DB7
FUNCTIONAL BLOCK DIAGRAM
VREF A
INPUT
BUFFER
LATCH
DAC A
DAC A/
DAC B
CS
WR
DGND
CONTROL
LOGIC
AD7528
LATCH
DAC B
RFB A
OUT A
AGND
RFB B
OUT B
GENERAL DESCRIPTION
The AD7528 is a monolithic dual 8-bit digital/analog converter
featuring excellent DAC-to-DAC matching. It is available in
skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount
packages.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
Data is transferred into either of the two DAC data latches via a
common 8-bit TTL/CMOS compatible input port. Control
input DAC A/DAC B determines which DAC is to be loaded.
The AD7528’s load cycle is similar to the write cycle of a ran-
dom access memory and the device is bus compatible with most
8-bit microprocessors, including 6800, 8080, 8085, Z80.
The device operates from a +5 V to +15 V power supply, dis-
sipating only 20 mW of power.
Both DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor for
each DAC.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC matching: since both of the AD7528 DACs are
fabricated at the same time on the same chip, precise match-
ing and tracking between DAC A and DAC B is inherent.
The AD7528’s matched CMOS DACs make a whole new
range of applications circuits possible, particularly in the
audio, graphics and process control areas.
2. Small package size: combining the inputs to the on-chip DAC
latches into a common data bus and adding a DAC A/DAC B
select line has allowed the AD7528 to be packaged in either a
small 20-lead DIP, SOIC or PLCC.
VREF B
ORDERING GUIDE1
Model2
Temperature
Ranges
Relative Gain Package
Accuracy Error Options3
AD7528JN
AD7528KN
AD7528LN
AD7528JP
AD7528KP
AD7528LP
AD7528JR
AD7528KR
AD7528LR
AD7528AQ
AD7528BQ
AD7528CQ
AD7528SQ
AD7528TQ
AD7528UQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
±1 LSB
±1/2 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±1 LSB
±1/2 LSB
±1/2 LSB
±4 LSB
±2 LSB
±1 LSB
±4 LSB
±2 LSB
±1 LSB
±4 LSB
±2 LSB
±1 LSB
±4 LSB
±2 LSB
±1 LSB
±4 LSB
±2 LSB
±1 LSB
N-20
N-20
N-20
P-20A
P-20A
P-20A
R-20
R-20
R-20
Q-20
Q-20
Q-20
Q-20
Q-20
Q-20
NOTES
1Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts
will be marked with cerdip designator “Q.”
2Processing to MIL-STD-883C, Class B is available. To order, add suffix “/883B” to
part number. For further information, see Analog Devices’ 1990 Military Products
Databook.
3N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998


Analog Devices Semiconductor Electronic Components Datasheet

AD7528 Datasheet

CMOS Dual 8-Bit Buffered Multiplying DAC

No Preview Available !

AD7528–SPECIFICATIONS (VREF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Temperature Coefficient3
Gain/Temperature
Output Leakage Current
OUT A (Pin 2)
OUT B (Pin 20)
Input Resistance (VREF A, VREF B)
VREF A/VREF B Input Resistance
Match
DIGITAL INPUTS4
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance
DB0–DB7
WR, CS, DAC A/DAC B
SWITCHING CHARACTERISTICS3
Chip Select to Write Set Up Time
tCS
Chip Select to Write Hold Time
tCH
DAC Select to Write Set Up Time
tAS
DAC Select to Write Hold Time
tAH
Data Valid to Write Set Up Time
tDS
Data Valid to Write Hold Time
tDH
Write Pulsewidth
tWR
POWER SUPPLY
IDD
Version1
VDD = +5 V
TA = +25°C TMIN, TMAX
VDD = +15 V
TA= +25°C TMIN, TMAX
Units
Test Conditions/Comments
All
J, A, S
K, B, T
L, C, U
All
J, A, S
K, B, T
L, C, U
8
±1
± 1/2
± 1/2
±1
±4
±2
±1
All ± 0.007
All ± 50
All ± 50
All 8
15
All ± 1
8
±1
± 1/2
± 1/2
±1
±6
±4
±3
± 0.007
± 400
± 400
8
15
±1
8
±1
± 1/2
± 1/2
±1
±4
±2
±1
8
±1
± 1/2
± 1/2
±1
±5
±3
±1
± 0.0035
± 50
± 50
8
15
±1
± 0.0035
± 200
± 200
8
15
±1
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
%/°C max
nA max
nA max
kmin
kmax
% max
This is an Endpoint Linearity Specification
All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Measured Using Internal RFB A and RFB B
Both DAC Latches Loaded with 11111111
Gain Error is Adjustable Using Circuits
of Figures 4 and 5
DAC Latches Loaded with 00000000
Input Resistance TC = –300 ppm/°C, Typical
Input Resistance is 11 k
All 2.4
All 0.8
All ± 1
All 10
All 15
All 90
All 0
All 90
All 0
All 80
All 0
All 90
All 2
All 100
2.4
0.8
± 10
10
15
100
0
100
0
90
0
100
2
500
13.5 13.5
1.5 1.5
± 1 ± 10
10 10
15 15
60 80
10 15
60 80
10 15
30 40
00
60 80
22
100 500
V min
V max
µA max
pF max
pF max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
mA max
µA max
VIN = 0 or VDD
See Timing Diagram
See Figure 3
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
AC
PERFORMANCE
CHARACTERISTICS5
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
Parameter
DC SUPPLY REJECTION (GAIN/VDD)
CURRENT SETTLING TIME2
PROPAGATION DELAY (From Digital In-
put to 90% of Final Analog Output Current)
DIGITAL-TO-ANALOG GLITCH IMPULSE
Version1
All
All
All
All
VDD = +5 V
VDD = +15 V
TA = +25°C TMIN, TMAX TA= +25°C TMIN, TMAX Units
0.02 0.04 0.01 0.02 % per % max
350 400 180 200 ns max
220 270 80 100 ns max
160 440 nV sec typ
Test Conditions/Comments
VDD = ± 5%
To 1/2 LSB. OUT A/OUT B Load = 100 .
WR = CS = 0 V. DB0–DB7 = 0 V to VDD or
VDD to 0 V
VREF A = VREF B = +10 V
OUT A, OUT B Load = 100 CEXT = 13 pF
WR = CS = 0 V DB0–DB7 = 0 V to VDD or
VDD to 0 V
For Code Transition 00000000 to 11111111
OUTPUT CAPACITANCE
COUTA
COUTB
COUTA
COUTB
All 50
50
120
120
50
50
50
pF max
DAC Latches Loaded with 00000000
50 50 50 pF max
120
120
120
pF max
DAC Latches Loaded with 11111111
120 120 120 pF max
AC FEEDTHROUGH6
VREF A to OUT A
VREF B to OUT B
All –70
–70
–65
–70
–65
dB max
VREF A, VREF B = 20 V p-p Sine Wave
–65
–70
–65
dB max
@ 100 kHz
–2– REV. B


Part Number AD7528
Description CMOS Dual 8-Bit Buffered Multiplying DAC
Maker Analog Devices
Total Page 8 Pages
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