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Analog Devices Semiconductor Electronic Components Datasheet

AD7477 Datasheet

1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23

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AD7477 pdf
a
1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
AD7476/AD7477/AD7478
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for VDD of 2.35 V to 5.25 V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high-speed, low-power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low-noise, wide bandwidth track/hold amplifier that can
handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipelined delays associated with the part.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low-power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN T/H
8-/10-/12-BIT
SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
SCLK
SDATA
CS
AD7476/AD7477/AD7478
GND
PRODUCT HIGHLIGHTS
1. First 12-/10-/8-bit ADCs in an SOT-23 package.
2. High Throughput with Low Power Consumption.
3. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock speed
increase. This allows the average power consumption to be
reduced while not converting. The part also features a shut-
down mode to maximize power efficiency at lower throughput
rates. Power consumption is 1 µA max when in shutdown.
4. Reference derived from the power supply.
5. No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000


Analog Devices Semiconductor Electronic Components Datasheet

AD7477 Datasheet

1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23

No Preview Available !

AD7477 pdf
AD7476/AD7477/AD7478
AD7476–SPECIFICATIONS1
(A Version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted;
S and B Versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1, 2 B Version1, 2 S Version1, 2 Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)3
Signal-to-Noise Ratio (SNR)3
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3
Intermodulation Distortion (IMD)3
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
69
70
70
–80
–82
–78
–78
10
30
6.5
DC ACCURACY
Resolution
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
Gain Error3
12
±1
± 0.75
± 0.5
± 0.5
70
71
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
± 1.5
± 1.5
69
70
70
–78
–80
–78
–78
10
30
6.5
12
± 1.5
± 0.6
–0.9/+1.5
± 0.75
±2
±2
dB min
dB min
dB min
dB typ
dB typ
fIN = 100 kHz Sine Wave
TA = 25°C
dB typ
dB typ
ns max
ps typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
S, B Versions, VDD = (2.35 V to 3.6 V)4;
A Version, VDD = (2.7 V to 3.6 V)
Guaranteed No Missed Codes to 12 Bits
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
±1
30
0 to VDD
±1
30
0 to VDD
±1
30
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN3, 5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3, 5
Output Coding
2.4 2.4
1.8 1.8
0.4 0.4
0.8 0.8
±1 ±1
±1 ±1
10 10
VDD – 0.2
0.4
VDD – 0.2
0.4
± 10 ± 10
10 10
Straight (Natural) Binary
2.4
1.8
0.4
0.8
±1
±1
10
VDD – 0.2
0.4
± 10
10
V min
V min
V max
V max
µA max
µA typ
pF max
V min
V max
µA max
pF max
VDD = 2.35 V
VDD = 3 V
VDD = 5 V
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200 µA; VDD = 2.35 V to 5.25 V
ISINK = 200 µA
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
0.8
1.33
1.33
µs max
Sixteen SCLK Cycles
500
500
500
ns max
Full-Scale Step Input
350
400
400
ns max
Sine Wave Input 100 kHz
1000
600
600
kSPS max See Serial Interface Section
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation7
Normal Mode (Operational)
Full Power-Down
2.35/5.25
2
1
3.5
1.6
1
80
17.5
4.8
5
3
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
2.35/5.25
2
1
3
1.4
1
80
15
4.2
5
3
V min/max
mA typ
mA typ
mA max
mA max
µA max
µA max
Digital I/Ps = 0 V or VDD
VDD = 4.75 V to 5.25 V. SCLK On or Off
VDD = 2.35 V to 3.6 V. SCLK On or Off
VDD = 4.75 V to 5.25 V. fSAMPLE = fSAMPLEMAX6
VDD = 2.35 V to 3.6 V. fSAMPLE = fSAMPLEMAX6
SCLK Off
SCLK On
mW max
mW max
µW max
µW max
VDD = 5 V. fSAMPLE = fSAMPLEMAX6
VDD = 3 V. fSAMPLE = fSAMPLEMAX6
VDD = 5 V. SCLK Off
VDD = 3 V. SCLK Off
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C, S Version: –55°C to +125°C.
2Operational from VDD = 2.0 V.
3See Terminology.
4Maximum B, S Versions specs apply as typical figures when VDD = 5.25 V.
5Sample tested at 25°C to ensure compliance.
6A Version: fSAMPLEMAX = 1 MSPS; B, S Versions: fSAMPLEMAX = 600 kSPS.
7See Power Versus Throughput Rate section.
Specifications subject to change without notice.
–2– REV. A


Part Number AD7477
Description 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
Maker Analog Devices
Total Page 16 Pages
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