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Analog Devices Semiconductor Electronic Components Datasheet

AD7468 Datasheet

1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23

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a
pecifications
1.8 V, Micro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
Preliminary Technical Data
AD7466/AD7467/AD7468
FEATURES
Specified for VDD of 1.8 V to 3.6 V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/µWire/DSP Compatible
Standby Mode: 0.5 µA max
6-Lead SOT-23 Package and 8 lead µSOIC
APPLICATIONS
Battery Powered Systems
Medical Instruments
Ramote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from VDD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to VDD. The
conversion rate is determined by the SCLK.
FUNCTIONAL BLOCK DIAGRAM
VDD
12/10/8-BIT
VIN T/H SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7466/67/68
GND
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT-23 package.
3. High Throughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
REV. PrC 07/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001


Analog Devices Semiconductor Electronic Components Datasheet

AD7468 Datasheet

1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23

No Preview Available !

pecifications
AD7466–SPECIFICATIONS1
(VDD = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; TA =
TMIN to TMAX, unless otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error3
Gain Error3
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN2,3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2,3
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Operational)
Power-Down
Power Dissipation4
Normal Mode (Operational)
Power-Down
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
B Version1, 2
70
71
–78
–80
–78
–78
10
30
TBD
TBD
Unit
dB min
dB min
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Test Conditions/Comments
fIN = 30 kHz Sine Wave
fa = 29.1 kHz, fb = 29.9 kHz
@ 3 dB
@ 0.1 dB
12
±1.5
±0.6
–0.9/+1.5
±0.75
±1.5
±1.5
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB max
Guaranteed No Missed Codes to 12 Bits
0 to VDD
±1
30
V
µA max
pF typ
0.7(VDD)
0.4
±1
±1
10
V min
V max
µA max
µA typ
pF max
VDD = 1.8 V to 3.6 V
Typically 10 nA, VIN = 0 V or VDD
VDD – 0.2
0.2
V min
V max
±10 µA max
10 pF max
Straight (Natural) Binary
ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V
ISINK = 200 µA
6.66
TBD
TBD
100
µs max Sixteen SCLK Cycles
ns max Full-Scale Step Input
ns max Sine Wave Input
kSPS max See Serial Interface Section
1.8/3.6
350
200
0.5
80
TBD
1.5
0.9
V min/max
µA max
µA max
Digital I/Ps = 0 V or VDD
VDD = 3 V. SCLK On or Off
VDD = 1.8 V. SCLK On or Off
µA max SCLK Off
µA max SCLK On
mW max
mW max
µW max
µW max
VDD = 3 V. fSAMPLE = TBD
VDD = 1.8 V. fSAMPLE = TBD
VDD = 3 V. SCLK Off
VDD = 1.8 V. SCLK Off
–2– REV. PrC


Part Number AD7468
Description 1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23
Maker Analog Devices
Total Page 15 Pages
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