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Analog Devices Semiconductor Electronic Components Datasheet

AD7450 Datasheet

Differential Input/ 1MSPS/ 12-Bit ADC in SO-8 and S0-8

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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Differential Input, 1MSPS,
12-Bit ADC in µSO-8 and S0-8
AD7450
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 3 V and 5 V
Low Power at max Throughput Rate:
3 mW typ at 833kSPS with 3 V Supplies
8 mW typ at 1MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPITM/QSPITM/
MicroWireTM/ DSP Compatible
Powerdown Mode: 1µA max
8 Pin µSOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
The AD7450 is a 12-bit, high speed, low power, succes-
sive-approximation (SAR) analog-to-digital converter
featuring a fully differential analog input. It operates from
a single 3 V or 5 V power supply and features throughput
rates up to 833kSPS or 1MSPS respectively.
This part contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage for the
AD7450 is applied externally to the VREF pin and can be
varied from 100 mV to 2.5 V depending on the power
supply and to suit the application. The value of the refer-
ence voltage determines the common mode voltage range
of the part. With this truly differential input structure and
variable reference input, the user can select a variety of
input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
MicroWire is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrJ 27/02/02
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN-
VREF
T/H
12-BIT SUCCESSIVE
APPROXIMATION
A DC
A D7450
CONTROL
LOGIC
SCLK
SDATA
CS
GND
The SAR architecture of this part ensures that there are
no pipeline delays.
The AD7450 uses advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with either 3 V or 5 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7450 offers 3mW typ power
consumption for 833kSPS throughput.
3.Fully Differential Analog Input.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. This
part also features a shutdown mode to maximize power
efficiency at lower throughput rates.
5.Variable Voltage Reference Input.
6.No Pipeline Delay.
7.Accurate control of the sampling instant via a CS input
and once off conversion control.
8. ENOB > 8 bits typ with 100mV Reference.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002


Analog Devices Semiconductor Electronic Components Datasheet

AD7450 Datasheet

Differential Input/ 1MSPS/ 12-Bit ADC in SO-8 and S0-8

No Preview Available !

PRELIMINARY TECHNICAL DATA
AD7450 - SPECIFICATIONS1
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1 B Version1 Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
(SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise2
Intermodulation Distortion (IMD)2
Second Order Terms
Third Order Terms
Aperture Delay3
Aperture Jitter3
Full Power Bandwidth3
Common Mode Rejection Ratio
(CMRR)2
70
-80
-80
-78
-78
10
50
20
2.5
TBD
70 dB min
-80 dB max
-80 dB max
-78
-78
10
50
20
2.5
TBD
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
dB
FIN = 300kHz Sine Wave,
fSAMPLE= 833kSPS, 1MSPS
@ -3 dB
@ -0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Zero Code Error2
Positive Gain Error2
Negative Gain Error2
12
±2
±1
±5
±5
±5
12 Bits
±1 LSB max
± 1 LSB max Guaranteed No Missed Codes to 12 Bits.
±5 LSB max
±5 LSB max
±5 LSB max
ANALOG INPUT
Full Scale Input Span
Absolute Input Voltage
VIN+
VIN-
DC Leakage Current
Input Capacitance
VIN+ - VIN -
VCM3 ± VREF/2
VCM3 ± VREF/2
±1 ±1
20 20
55
Volts
Volts
Volts
µA max
pF typ
pF typ
2 x VREF4
VCM = VREF
VCM = VREF
When in Track
When in Hold
REFERENCE INPUT
VREF Input Voltage
2.55
1.256
2.5 Volts
1.25 Volts
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN7
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance7
Output Coding
±1 ±1 µA max
15 15 pF typ
2.4 2.4 V min
0.8 0.8 V max
±1 ±1 µA max
10 10 pF max
2.8 2.8
0.4 0.4
±10 ±10
10 10
Two’s Complement
V min
V max
µA max
pF max
5 V supply (±1% tolerance for specified
performance)
3 V supply (±1% tolerance for specified
performance)
Typically 10 nA, VIN = 0 V or VDD
ISOURCE = 200µA
ISINK =200µA
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time8
Throughput Rate9
16
275
1
833
16 SCLK cycles 888ns with an 18MHz SCLK
1.07µs with a 15MHz SCLK
275 ns max
Sine Wave input
1 MSPS max @ VDD = 5V
833 kSPS max @ VDD = 3V
–2– REV. PrJ


Part Number AD7450
Description Differential Input/ 1MSPS/ 12-Bit ADC in SO-8 and S0-8
Maker Analog Devices
Total Page 24 Pages
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