Description
The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVD
Features
- SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (.
- 1.0 dBFS) SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (.
- 1.0 dBFS) Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical Integrated 16k × 12 FIFO FIFO readback options
12-bit parallel CMOS at 62.5 MHz 6-bit DDR LVDS interface SPORT at 62.5 MHz SPI at 25 MHz High speed synchronization capability 1 GHz full power analog bandwidth Integrated input buffer On-chip refer.
AD6641 Datasheet
