AD6641
FEATURES
SNR = 65.8 d BFS at f IN up to 250 MHz at 500 MSPS ENOB of 10.5 bits at f IN up to 250 MHz at 500 MSPS (- 1.0 d BFS) SFDR = 80 d Bc at f IN up to 250 MHz at 500 MSPS (- 1.0 d BFS) Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical Integrated 16k × 12 FIFO FIFO readback options
12-bit parallel CMOS at 62.5 MHz 6-bit DDR LVDS interface SPORT at 62.5 MHz SPI at 25 MHz High speed synchronization capability 1 GHz full power analog bandwidth Integrated input buffer On-chip reference, no external decoupling required Low power dissipation 695 m W at 500 MSPS Programmable input voltage range 1.18 V to 1.6 V, 1.5 V nominal 1.9 V analog and digital supply operation 1.9 V or 3.3 V SPI and SPORT operation Clock duty cycle stabilizer Integrated data clock output with programmable clock and data alignment
GENERAL DESCRIPTION
The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back...
