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AD14060L - DSP Multiprocessor

Download the AD14060L datasheet PDF. This datasheet also covers the AD14060 variant, as both devices belong to the same dsp multiprocessor family and are provided as variant models within a single manufacturer datasheet.

General Description

The AD14060/AD14060L Quad-SHARC is the first in a family of high performance DSP multiprocessor modules.

The core of the multiprocessor is the ADSP-21060 DSP microcomputer.

The AD14060/AD14060L has the highest performance-to-density and lowest cost-to-performance ratios of any in its class.

Key Features

  • ADSP-21060 core processor ( × 4) 480 MFLOPS peak, 320 MFLOPS sustained 25 ns instruction rate, single-cycle instruction execution.
  • each of four processors 16 Mbit shared SRAM (internal to SHARCs) 4 gigawords addressable off-module memory Twelve 40 Mbyte/s link ports (3 per SHARC) Four 40 Mbit/s independent serial ports (one from each SHARC) One 40 Mbit/s common serial port 5 V and 3.3 V operation 32-bit single precision and 40-bit extended precision IEEE floating point data formats, or 32.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AD14060-AnalogDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Analog Devices

Part Number Description
AD14060 DSP Multiprocessor
AD1403 Low Cost/ Precision 2.5 V IC References
AD1403A Low Cost/ Precision 2.5 V IC References
AD14160 DSP Multiprocessor
AD14160L DSP Multiprocessor

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PERFORMANCE FEATURES ADSP-21060 core processor ( × 4) 480 MFLOPS peak, 320 MFLOPS sustained 25 ns instruction rate, single-cycle instruction execution—each of four processors 16 Mbit shared SRAM (internal to SHARCs) 4 gigawords addressable off-module memory Twelve 40 Mbyte/s link ports (3 per SHARC) Four 40 Mbit/s independent serial ports (one from each SHARC) One 40 Mbit/s common serial port 5 V and 3.3 V operation 32-bit single precision and 40-bit extended precision IEEE floating point data formats, or 32-bit fixed point data format IEEE JTAG Standard 1149.1 test access port and on-chip emulation PACKAGING FEATURES 308-lead ceramic quad flatpack (CQFP) 2.05" (52 mm) body size Cavity up or down, configurable Low profile, 0.160" height Hermetic 25 Mil (0.