ASM3P2531A
Features
FCC approved method of EMI attenuation. Generates a low EMI spread spectrum of the input clock frequency. Optimized for input frequency range between 35MHz
- 55MHz. Internal loop filter minimizes external ponents and board space. Frequency Deviation: ±1.65%. Low inherent cycle-to-cycle jitter. 3.3 V or 5 V operating voltage. CMOS/TTL patible inputs and outputs. Ultra low power CMOS design: 5.50 m A @3.3 V. Supports notebook VGA and other LCD timing controller applications. Available in 8-pin SOIC and TSSOP. dependent signals. It allows significant system cost savings by reducing the number of circuit board layers and shielding traditionally required to pass EMI regulations. The ASM3P2531A modulates the output of a single PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI pared to the typical narrow band signal produced by oscillators and most clock generators....
