AS7C251MNTF18A sram equivalent, 2.5v 1m x 18 flowthrough synchronous sram.
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* Organization: 1,048,576 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.5/1.
requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing.
The AS7C251MNTF18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 18 bits and incorporates a LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Dela.
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