ƒ ƒ ƒ ƒ Fully Integrated PLL Up to 200MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance ASM5I961C reference clock while the ASM5I961P offers an LVPECL .

The ASM5I961 is offered with two different configurations. The ASM5I961C offers an LVCMOS Block Diagram Q0 CCLK 50K .

The ASM5I961C is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150pS the device meets the needs of the most demanding clock tree applications. The ASM5I961 is offered with two di.

ASM5I961P

ASM5I9653A

ASM5I9658

ASM5I9350

ASM5I9351

ASM5I9352

ASM5I9772A

ASM5I9773A

ASM5I9774A

ASM5I9775A

ASM5I2304A

ASM5I2304B

ASM5I2305A

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