AS8C803601 Datasheet | Alliance Semiconductor

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs - AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations - The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal and can be (3.8ns Clock-to-Data Access) - ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time. - Internally synchronized output buffer enable...