AS7C4096 Datasheet | Alliance Semiconductor

Features - AS7C4096 (5V version) - AS7C34096 (3.3V version) - Industrial and mercial temperature - Organization: 524,288 words × 8 bits - Center power and ground pins - High speed - 10/12/15/20 ns address access time - 5/6/7/9 ns output enable access time - Low power consumption: ACTIVE - 1375 m W (AS7C4096) / max @ 12 ns - 468 m W (AS7C34096) / max @ 12 ns - Low power consumption: STANDBY - 110 m W (AS7C4096) / max CMOS - 72 m W (AS7C34096) / max CMOS - 2.0V data retention - Equal access and cycle times - Easy memory expansion with CE, OE inputs - TTL-patible, three-state I/O - JEDEC standard packages - 400 mil 36-pin SOJ - 400 mil 44-pin TSOP II - ESD protection ≥ 2000 volts - Latch-up current ≥ 200 m A Row decoder Sense amp Logic block diagram VCC GND Input buffer A0 A1 A2 A3 524,288 × 8 A4 A5 Array A6 (4,194,304) A7 A8 A9 Column decoder Control...