* Fast access time from clock: 5.4/5.4 ns
* Fast clock rate: 166/143 MHz
* Fully synchronous operation
* Internal pipelined architecture
* Four intern.

requiring high memory bandwidth. Table 1. Key Specifications AS4C4M32S tCK3 Clock Cycle time(min.) tAC3 Access time fro.

Table 1. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. C.

AS4C4M16D1A

AS4C4M16S

AS4C4M16SA

AS4C4M16SA-C

AS4C4M16SA-I

AS4C4M4

AS4C4M4E0

AS4C4M4E1

AS4C4M4F0

AS4C4M4F1

AS4C4067

AS4C4256

AS4C4256883C

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