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OR2C12A - Field-Programmable Gate Arrays

Download the OR2C12A datasheet PDF. This datasheet also covers the OR2 variant, as both devices belong to the same field-programmable gate arrays family and are provided as variant models within a single manufacturer datasheet.

Description

3 ORCA Foundry Development System Overview 5 Architecture 5 Programmable Logic Cells 5 Programmable Function Unit 5 Look-Up Table Operating Modes 7 Latches/Flip-Flops 15 PLC Routing Resources 17 PLC Architectural Description 22 Programmable Input/Output Cells 25 Inputs 25 Outputs 26 5 V Tol

Features

  • s s s s s s s s s s s High-performance, cost-effective, low-power 0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis) Four 1.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (OR2-C04A.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number OR2C12A
Manufacturer Agere Systems
File Size 3.07 MB
Description Field-Programmable Gate Arrays
Datasheet download datasheet OR2C12A Datasheet

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Other Datasheets by Agere Systems

Part Number Description
OR2C10A Field-Programmable Gate Arrays
OR2C15A Field-Programmable Gate Arrays
OR2C04A Field-Programmable Gate Arrays
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OR2C08A Field-Programmable Gate Arrays

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data Sheet June 1999 ORCA® Series 2 Field-Programmable Gate Arrays Features s s s s s s s s s s s High-performance, cost-effective, low-power 0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed grade) High density (up to 43,200 usable, logic-only gates; or 99,400 gates including RAM) Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow interconnection to both 3.
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