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Agere Systems

L8567 Datasheet Preview

L8567 Datasheet

SLIC

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Data Sheet
August 1999
L8567 SLIC for
People’s Republic of China Applications
Features
s Low active power (typical 149 mW during on-hook
transmission)
s Sleep state for low idle power (47 mW typical)
s Quiet tip/ring polarity reversal
s Distortion-free on-hook transmission
s –35 V to –65 V battery operation
s Convenient operating states:
— Forward active
— Polarity reversal active
— Sleep
— Forward disconnect
s Supervision functions:
— Fixed threshold off-hook detector with
longitudinal rejection and hysteresis
— Ring trip detector
— Thermal shutdown indication
s Adjustable loop current limit
s Three driver outputs for relay driver
s LED driver output to indicate off-hook
s Latched parallel data interface
s Battery and +5 V required:
— Optional auxiliary lower voltage battery to
reduce short loop power
s –40 °C to +85 °C operational temperature range
s User-selectable power management techniques
s Thermal protection
s 32-pin PLCC or 44-pin PLCC packaging
Description
General
This electronic subscriber loop interface circuit
(SLIC) is optimized for low cost and low power con-
sumption while providing a full-feature set.
Included in the feature set is quiet reverse battery.
Quiet polarity reversal is possible because the ac
path is uninterrupted during transmission. The dc
loop current limit is user-adjustable via a single exter-
nal resistor. The maximum battery voltage is speci-
fied as –65 V for long loop applications. The L8567
supports on-hook transmission.
The total short loop off-hook power may be reduced
by use of a lower-voltage auxiliary battery supply. If,
when using the 32-pin PLCC, the user does not wish
to supply an auxiliary battery, the component of the
total short loop off-hook power that is dissipated on
the L8567 SLIC is controlled by use of an external
power resistor. With the 44-pin PLCC, a power resis-
tor is not necessary.
Included are both the loop closure and ring trip
supervision functions. The loop closure threshold is
fixed internally, which eliminates the need for an
external precision resistor to set the threshold. To
minimize noise at the supervision output, hysteresis
is included on the loop closure function. The loop clo-
sure and ring trip outputs are multiplexed into a sin-
gle NSTAT output. Also included is a thermal
shutdown mechanism. If device temperature exceeds
165 °C, as may be the case under an extended
power cross fault, the SLIC will shut down (i.e., enter
a high-impedance state) to provide protection against
the fault. A logic output will indicate the SLIC is in
thermal shutdown.




Agere Systems

L8567 Datasheet Preview

L8567 Datasheet

SLIC

No Preview Available !

L8567 SLIC for
People’s Republic of China Applications
Data Sheet
August 1999
Table of Contents
Contents
Page
Features ......................................................................1
Description...................................................................1
General...................................................................1
Application for People’s Republic of China ............4
Pin Information ............................................................6
Coding Information ......................................................9
Absolute Maximum Ratings.......................................11
Recommended Operating Conditions .......................11
Electrical Characteristics ...........................................12
Logic Interface .....................................................14
Ring Trip Requirements .......................................16
Test Configurations ...................................................17
RFI Rejection........................................................19
Functional Description ...............................................21
General.................................................................21
Use with T7507 Codec for Use in People’s
Republic of China ..............................................21
Chip Set Performance Specifications ........................22
Gain ......................................................................22
Gain Flatness—In Band .......................................22
Gain Flatness—Out of Band—High
Frequencies .......................................................22
Gain Flatness—Out of Band—Low
Frequencies .......................................................22
Loss vs. Level Relative to Loss at –10 dBm
Input at 1020 Hz ................................................23
Return Loss ..........................................................23
Hybrid Balance .....................................................23
Applications ...............................................................24
Design Considerations .........................................26
Characteristic Curves ...........................................27
Power Control.......................................................28
Power Control—Auxiliary Battery .........................29
Power Control—32-Pin PLCC with Power
Control Resistor .................................................29
Power Considerations ..........................................30
Power Control—44-Pin PLCC Package ...............32
dc Characteristics ......................................................33
Loop Range..........................................................34
dc Applications ..........................................................34
On-Hook Transmission.........................................34
Supervision...........................................................35
Loop Closure ........................................................35
Ring Trip Detection...............................................36
Other Supervision Functions ................................36
Latched Parallel Data Interface ............................37
ac Design .............................................................38
First-Generation Codecs ......................................38
Second-Generation Codecs .................................38
Third-Generation Codecs .....................................38
T7507 Codec........................................................38
Outline Diagrams.......................................................39
32-Pin PLCC ........................................................39
44-Pin PLCC ........................................................40
Ordering Information..................................................41
Figures
Page
Figure 1. Functional Diagram .....................................5
Figure 2. 32-Pin Diagram (PLCC Chip) ......................6
Figure 3. 44-Pin Diagram (PLCC Chip) ......................6
Figure 4. Ring Trip Circuits .......................................16
Figure 5. Timing Requirements ................................16
Figure 6. Basic Test Circuit ......................................17
Figure 7. Metallic PSRR ...........................................18
Figure 8. Longitudinal PSRR ....................................18
Figure 9. Longitudinal Balance .................................18
Figure 10. Longitudinal Impedance ..........................18
Figure 11. ac Gains ..................................................18
Figure 12. RFI Rejection Test Circuit .......................19
Figure 13. RFI Testing, Forward Battery,
600 Loop, No Capacitor, 1 Vrms .........20
Figure 14. RFI Testing, Forward Battery,
600 Loop, No Capacitor, 2 Vrms .........20
Figure 15. Termination Impedance ...........................22
Figure 16. Transmit and Receive Direction
Frequency-Dependent Loss Relative
to Gain at 3400 Hz ..................................22
Figure 17. Loss vs. Level ..........................................23
Figure 18. Return Loss .............................................23
Figure 19. Hybrid Balance ........................................23
Figure 20. Basic Loop Start Application Using
T7507 Codec and L7583 Switch for
200 + (680 || 100 nF) Complex
Termination and Hybrid Balance .............24
Figure 21. L8567 Typical VCC Power Supply
Rejection .................................................27
Figure 22. L8567 Typical VBAT Power Supply
Rejection .................................................27
Figure 23. L8567 Loop Current vs. Loop Voltage .....27
Figure 24. L8567 Loop/Battery Current (with Battery
Switch) vs. Loop Resistance ...................27
Figure 25. Power Derating ........................................28
Figure 26. Tip/Ring Voltage Decrease .....................33
Figure 27. SLIC 2-Wire Output Stage .......................34
Figure 28. Ring Trip Equivalent Circuit and
Equivalent Application .............................36
Figure 29. Simplified Control Scheme ......................37
Figure 30. Logic Output Latches .............................. 38
2 Lucent Technologies Inc.


Part Number L8567
Description SLIC
Maker Agere Systems
Total Page 30 Pages
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