UT9Q512K32E Datasheet | Aeroflex Circuit Technology

Standard Products UT9Q512K32E 16 Megabit Rad Tolerant SRAM MCM Data Sheet June 28, 2011 Features  25ns maximum (5 volt supply) address access time  Asynchronous operation for patible with industry standard 512K x 8 SRAMs  TTL patible inputs and output levels, three-state bidirectional data bus  Operational environment: - Total dose: 50 krads(Si) - SEL Immune >110 Me V-cm2/mg - LETTH(0.25) = >52 Me V-cm2/mg - Saturated Cross Section (cm2) per bit, 2.8E-8 - <1.1E-9 errors/bit-day, Adams 90% geosynchronous heavy ion  Packaging: - 68-lead dual cavity ceramic quad flatpack (CQFP) (11.0 grams)  Standard Microcircuit Drawing 5962-01511 - QML Q and Vpliant part INTRODUCTION The UT9Q512K32E Rad Tol product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a mon output enable. Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. Writing to each memory is acplished by taking chip enable (En) input LOW and write enable (Wn) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is acplished by taking chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a mon input to any bination of the discrete memory die. W3 E3 W2 E2 W1 E1 W0 E0 A(18:0) 512K x 8 512K x 8 512K x 8 512K x 8 DQ(31:24)...