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54ACS164245S Datasheet Preview

54ACS164245S Datasheet

UT54ACS164245S

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UT54ACS164245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
April , 2002
FEATURES
Voltage translation
www.DataShee-t45UV.cobmus to 3.3V bus
- 3.3V bus to 5V bus
Cold sparing
- 1Mminimum input impedance power-off
• 0.6µm Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
High speed, low power consumption
Schmitt trigger inputs to filter noisy signals
Available QML Q or V processes
Standard Microcircuit Drawing 5962-98580
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACS164245S MultiPurpose transceiver
is built using UTMC’s Commercial RadHardTM epitaxial
CMOS technology and is ideal for space applications. This high
speed, low power UT54ACS164245S transceiver is designed to
perform multiple functions including: asynchronous two-way
communication, signal buffering, voltage translation, and cold
sparing. With VDD equal to zero volts, the UT54ACS164245S
outputs and inputs present a minimum impedance of 1Mmak-
ing it ideal for "cold spare" applications. Balanced outputs and
low "on" output impedance make the UT54ACS164245S well
suited for driving high capacitance loads and low impedance
backplanes. The UT54ACS164245S enables system designers
to interface 3.3 volt CMOS compatible components with 5 volt
CMOS components. For voltage translation, the A port inter-
faces with the 3.3 volt bus; the B port interfaces with the 5 volt
bus. The direction control (DIRx) controls the direction of data
flow. The output enable (OEx) overrides the direction control
and disables both ports. These signals can be driven from either
port A or B. The direction and output enable controls operate
these devices as either two independent 8-bit transceivers or one
16-bit transceiver.
LOGIC SYMBOL
O E1 (48)
O E2 (25)
(1)
DIR1
G1
G2 2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
(47)
1A1
(46)
1A2
(44)
1A3
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
(35)
2A2
(33)
2A3
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
11
12
21
22
(24)
DIR2
(2)
1B1
(3)
1B2
(5)
1B3
(6)
1B4
(8)
1B5
(9)
(11) 1B6
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
PIN DESCRIPTION
Pin Names
Description
OE x
Output Enable Input (Active Low)
DIRx
Direction Control Inputs
xAx Side A Inputs or 3-State Outputs (3.3V Port)
xBx Side B Inputs or 3-State Outputs (5V Port)
FUNCTION TABLE
ENABLE
OE x
L
DIRECTION
DIRx
L
LH
HX
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
1




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54ACS164245S Datasheet Preview

54ACS164245S Datasheet

UT54ACS164245S

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PINOUTS
DIR1
1B1
1B2
VSS
www.DataSheet4U.com1B3
1B4
VDD1
1B5
1B6
VSS
1B7
1B8
2B1
2B2
VSS
2B3
2B4
VDD1
2B5
2B6
VSS
2B7
2B8
DIR2
48-Lead Flatpack
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
OE1
1A1
1A2
VSS
1A3
1A4
VDD2
1A5
1A6
VSS
1A7
1A8
2A1
2A2
VSS
2A3
2A4
VDD2
2A5
2A6
VSS
2A7
2A8
O E2
POWER TABLE1
Port B
5 Volts
5 Volts
3.3 Volts
VSS
VSS
Port A
3.3 Volts
5 Volts
3.3 Volts
VSS
3.3V or 5V
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port B Cold Spare
NOTE:
1. V DD2 cannot be tied to V SS while power is applied to VDD1.
Control signals DIRx and OEx are 5 volt tolerant inputs. When
VDD2 is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can
be applied to all control inputs. For proper operation connect
power to all VDD and ground all V SS pins (i.e., no floating VDD
or VSS input pins). Tie unused inputs to VSS. If VDD1 and
VDD2 are not powered up together, then VDD2 should be pow-
ered up first for proper control of OE and DIR. Until VDD2
reaches 2.75V + 5%, control of the outputs byOE and DIR can-
not be guaranteed. During operation of the part, after power up,
insure VDD1 > VDD2. Tie unused inputs to VSS.
2


Part Number 54ACS164245S
Description UT54ACS164245S
Maker Aeroflex Circuit Technology
Total Page 14 Pages
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