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Adronic Components

PE12316 Datasheet Preview

PE12316 Datasheet

Triple Incremental Encoder

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February 6, 2003 Preliminary (Version 1.1)
Features:
Functional and pincompatible with TI
CF32006 / THCT12316
Three independent channels in one device
Each channel compatible with PE12016
Available as IP-Core or within PLCC68
Package
Interfaces three mechanisms / axes to data
bus
Pulse width measurement
Frequency measurement
PE12316
Triple
Incremental Encoder
Cascadable 16-bit counters
TTL compatible
5V and 3.3V Operation
8 Bit parallel tristatable Bus
Simple read & write procedure
High speed 20 MHz clock operation
Direction discriminators identify &
measure forward/backward rotation
separate zero pulse input
New Feature:
Each channel extendable to 24 Bit
A1
A2
CS
GND
D0
D1
VCC
D2
D3
GND
D4
D5
VCC
D6
D7
GND
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PE12316
PLCC68
60 KLI-KLO3
59 CARRY1
58 BORROW1
57 CARRY2
56 BORROW2
55 CARRY3
54 BORROW3
53 GND
52 VCC
51 DOWN3
50 UP3
49 DOWN2
48 UP2
47 DOWN1
46 UP1
45 Ua23
44 Ua13
Figure 1 Pinout
NC Pins should be left open
and not connected to the
PCB. They are reserved for
future upgrades.
Description:
The PE12316 TRIPLE INCREMENTAL ENCODER INTERFACE consists of three channels each,
which can independently determine the direction of displacement of a mechanical or axis based device
on two input signals from transducers in quadrature. Alternatively, each channel can measure a pulse
width using a known clock rate, or a frequency, by counting input pulses over a known time interval. It
includes three 16/24-bit counters which may also be used separately. The PE12316 may be cascaded
between channels on one device or between devices to provide accuracy greater than 16/24-bits, and
is designed for use in many microprocessor-based systems.
February 6, 2003 (Preliminary Version 1.1)
Page 1/29
PE12316
Free Datasheet http://www.Datasheet4U.com




Adronic Components

PE12316 Datasheet Preview

PE12316 Datasheet

Triple Incremental Encoder

No Preview Available !

February 6, 2003 Preliminary (Version 1.1)
PE12316
Triple
Incremental Encoder
Availability:
The PE12316 is available as a replacement IC or
Netlist IP Core, fully compatible with the TI
CF32006 functionality. The replacement IC is
packaged within the popular PLCC68.
The IP Core can be targeted to any desired
FPGA/CPLD or ASIC Technology and is
delivered within the according netlist format. The
database has been proven in a co-emulation
together with the reference part by stimulating
both devices with the same inputs and observing
the identical results on the outputs.
Ressource Usage IP Core:
Gate count for ASIC Technologies is
approximately 7000 Gates.
For FPGAs a technology with at least 20.000
FPGA Gates like XCS20 from Xilinx needs to be
chosen.
Enhancements over CF32006:
The PE12316 has 3 counters with 24 Bit
internally. Therefore an additional addressline
/A3 is introduced on pin 6 to select the Bits 16-
23 of each channel in conjunction with the other
addressbits A0-A2.
NOTE: If /A3 is left unconnected, PE12316 is
identical to CF32006.
Differences:
The PE12316 has some slight changes:
UA1X and UA2X are synchronized with the
clock, eliminating the need to place a discrete
ACT74 type Flipflop in front of these signals.
Due to this feature a latency of one clock cycle is
introduced, resulting worst case in a +/-1 counter
difference.
February 6, 2003 (Preliminary Version 1.1)
Page 2/29
PE12316
Free Datasheet http://www.Datasheet4U.com


Part Number PE12316
Description Triple Incremental Encoder
Maker Adronic Components
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