AT91SAM7S512
Key Features
- Incorporates the ARM7TDMI® ARM® Thumb® Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
- Internal High-speed Flash - 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes (Dual Plane) - 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane) - 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) - 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) - 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) - 16 Kbytes (SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane) - Single Cycle Access at Up to 30 MHz in Worst Case Conditions - Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed - Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms - 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit - Fast Flash Programming Interface for High Volume Production
- Internal High-speed SRAM, Single-cycle Access at Maximum Speed - 64 Kbytes (SAM7S512/256) - 32 Kbytes (SAM7S128) - 16 Kbytes (SAM7S64) - 8 Kbytes (SAM7S321/32) - 4 Kbytes (SAM7S161/16)
- Memory Controller (MC) - Embedded Flash Controller, Abort Status and Misalignment Detection
- Reset Controller (RSTC) - Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector - Provides External Reset Signal Shaping and Reset Source Status
- Clock Generator (CKGR) - Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
- Power Management Controller (PMC) - Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode - Three Programmable Extern
