AT78C5090 Datasheet | Atmel

.. Features - 1.5 Gbps Bi-directional Transceiver - pliant with Serial ATA Gen1 Revision 1.0a Specification - Low Power Operation - 75 m W per Channel Nominal - Key Blocks Include - Integrated OOB Processor - K28.5 MA Detection - Digital Clock and Data Recovery (CDR) with Digital Equalization - Spread Spectrum Clocking - Optional 8B/10B Encoder and Decoder - Parallel I/O - Synchronous 8-bit/10-bit Parallel Interface @ 150 MHz - Serial I/0 - Programmable Pre-emphasis - Programmable Swing Control - Passive Equalization in Receive Input Buffer - Support for Spread Spectrum Clocking - Integrated 100Ω Matched Differential Termination - AC and DC Coupling Support - Test Features - Far-end and Near-end Loopback Support - At Speed BIST - Scan Test of Physical Coding Sub-layer (PCS) 2-channel Serial ATA PHY AT78C5090 Summary Overview The AT78C5090 is a 2-channel SATA PHY supporting Gen 1 speeds of 1.5 Gbps. The IP has been designed based on the requirements stated in the Serial ATA Standard, Rev 1.0a, Jan 2003. On the transmit path, parallel data is registered, passed through a transmit FIFO to pensate for phase differences between the link and PHY clocks, 8B/10B encoded and then passed out via a high speed serializer using a spread spectrum clock. Builtin flexibility permits bypassing the encoding block in addition to optionally disabling the spread spectrum clocking. The user can control the transmit buffer output swing and pre-emphasis levels via direct input signals. On the receive path, the AT78C5090 performs the serial-to-parallel conversion, using a high bandwidth clock and data recovery (CDR) block. The recovered data is then passed through a ma alignment block and an optional 8B/10B decode block before being passed to the phy Ctrl layer via a parallel interface. This interface is synchronous to the recovered clock. The PHY core has an out of band (OOB) processor. As specified by the Serial ATA standard, three out of band (OOB)...