Datasheet Summary
Features
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- SPARC V8 High Performance Low-power 32-bit Architecture
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- - LEON2-FT 1.0.13 pliant
- 8 Register Windows Advanced Architecture:
- On-chip Amba Bus
- 5 Stage Pipeline
- 16 kbyte Multi-sets Data Cache
- 32 kbyte Multi-sets Instruction Cache On-chip Peripherals:
- Memory Interface PROM Controller SRAM Controller SDRAM Controller
- Timers Two 24-bit Timers Watchdog Timer
- Two 8-bit UARTs
- Interrupt Controller with 4 External Programmable Inputs
- 32 Parallel I/O Interface
- 33MHz PCI Interface pliant with 2.2 PCI Specification Integrated 32/64-bit IEEE 754 Floating-point Unit Fault Tolerance by Design
- Full Triple Modular...