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ASI

MT5C2565 Datasheet Preview

MT5C2565 Datasheet

64K x 4 SRAM MEMORY ARRAY

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Austin Semiconductor, Inc.
SRAM
MT5C2565
64K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-89524
• MIL-STD-883
FEATURES
• High Speed: 12, 15, 20, 25, 35, and 45ns
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-15
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (300 mil)
Ceramic LCC
C No.108
EC No. 204
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(300 MIL)
NC 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
CE\ 12
OE\ 13
Vss 14
28 Vcc
27 A15
26 A14
25 A13
24 A12
23 A11
22 A10
21 NC
20 NC
19 DQ4
18 DQ3
17 DQ2
16 DQ1
15 WE\
28-Pin LCC (EC)
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 1 0
A9 1 1
CE\ 1 2
3 2 1 28 27
2 6 A15
2 5 A14
2 4 A13
2 3 A12
2 2 A11
2 1 A10
2 0 DQ4
1 9 DQ3
1 8 DQ2
13 14 15 16 17
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) and output
enable (OE\) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable
(WE\) and CE\ inputs are both LOW. Reading is accomplished
when WE\ remains HIGH and CE\ and OE\ go LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power
requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (ISBC2) over the standard
version.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1




ASI

MT5C2565 Datasheet Preview

MT5C2565 Datasheet

64K x 4 SRAM MEMORY ARRAY

No Preview Available !

Austin Semiconductor, Inc.
SRAM
MT5C2565
A12 A11
A11 A10
A10 A12
A8 A8
A3 A3
A2 A2
A1 A1
A0 A0
(LCC)
FUNCTIONAL BLOCK DIAGRAM
VCC GND
262,144-BIT
MEMORY ARRAY
(LSB)
COLUMN DECODER
(LSB)
A7 A6 A5 A4 A9 A15 A14 A13
POWER
DOWN
DQ4
DQ1
CE\
OE\
WE\
TRUTH TABLE
MODE
OE\ CE\ WE\
DQ
POWER
STANDBY X H X HIGH-Z STANDBY
READ
LLH
Q ACTIVE
READ
H L H HIGH-Z ACTIVE
WRITE
XL L
D ACTIVE
MT5C2565
Rev. 1.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2


Part Number MT5C2565
Description 64K x 4 SRAM MEMORY ARRAY
Maker ASI
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MT5C2565 Datasheet PDF






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