A67P1618A Datasheet | AMIC Technology

A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Document Title 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. History 0.0 Initial issue Issue Date May 12, 2008 Remark Preliminary PRELIMINARY (May, 2008, Version 0.0) AMIC Technology, Corp. A67P1618A/A67P0636A Series Preliminary 2M X 18, 1M X 36 LVTTL, Pipelined ZeBLTM SRAM Features - Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) - Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization - Signal +2.5V ± 5% power supply - Individual Byte Write control capability - Clock enable ( CEN) pin to enable clock and suspend operations -...