A67L06181 Datasheet - AMIC Technology

A67L06181 Flow-through ZeBL SRAM

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L06181, A67L93361 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 10.

A67L06181 Features

* Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered addr

A67L06181 Datasheet (244.27 KB)