TD02 array equivalent, cmos gate array.
TD0x is a family of non-inverting time delays.
Logic Symbol
Truth Table
TD0x
Delay
AQ LL HH
HDL Syntax Verilog .................... TD0x inst_name (Q, A); VHDL...................... inst_name: TD0x port map (Q, A);
Pin Loading Pin Name A
TD02.
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