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PLD3 Datasheet Preview

PLD3 Datasheet

CMOS Gate Array

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®
Description
PLD3 is an active pull-down buffer piece.
Logic Symbol
Truth Table
PLD3
PADM
N/A
3/'
$0,+*  PLFURQ &026 *DWH $UUD\
Pin Loading
N/A
HDL Syntax
Verilog .................... PLD3 inst_name (PADM);
VHDL...................... inst_name: PLD3 port map (PADM);
Power Characteristics
Parameter
Static IDD (TJ = 85°C)
EQLpd
See page 2-15 for power equation.
Value
TBD
149.8
Units
nA
Eq-load
4-51


Part Number PLD3
Description CMOS Gate Array
Maker AMI
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PLD3 Datasheet PDF






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