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PLD3 - CMOS Gate Array

General Description

PLD3 is an active pull-down buffer piece.

 PLFURQ &026 DWH $UUD Pin Loading N/A HDL Syntax Verilog PLD3 inst_name (PADM); VHDL inst_name: PLD3 port map (PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See pag

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Datasheet Details

Part number PLD3
Manufacturer AMI
File Size 16.44 KB
Description CMOS Gate Array
Datasheet download datasheet PLD3 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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® Description PLD3 is an active pull-down buffer piece. Logic Symbol Truth Table PLD3 PADM N/A 3/' $0,+*  PLFURQ &026 *DWH $UUD Pin Loading N/A HDL Syntax Verilog .................... PLD3 inst_name (PADM); VHDL...................... inst_name: PLD3 port map (PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 149.