PLD3 array equivalent, cmos gate array.
PLD3 is an active pull-down buffer piece.
Logic Symbol
Truth Table
PLD3
PADM
N/A
3/'
$0,+* PLFURQ &026 *DWH $UUD
Pin Loading
N/A
HDL Syntax Verilog .................... PLD3 inst_name (PADM); VHDL...................... inst_name: PLD3 po.
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