ODTSXX12
Description
ODTSXXxx is a family of 4 to 24 m A, non-inverting, TTL-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXXxx A SL
PADM
A PADM LL HH
HDL Syntax Verilog ODTSXXxx inst_name (PADM, A); VHDL inst_name: ODTSXXxx port map (PADM, A);
Pin Loading
Pin Name A (eq-load)
ODTSXX04 9.3
Power Characteristics
Cell Output Drive (m A)
ODTSXX04
ODTSXX08
ODTSXX16
ODTSXX24
24 a. See page 2-15 for power equation.
ODTSXX08 9.3
Load ODTSXX12
ODTSXX16 9.3
Power Characteristicsa
Static IDD (TJ = 85°C) (n A) TBD
EQLpd (Eq-load) 198.6
ODTSXX24 11.4
Pad Logic
4-42
®
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (p F)
ODTSXX04
From: A t PLH
To: PADM t PLH
1.51...
