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ODTSXN04 - CMOS Gate Array

Description

ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pulldown) and controlled slew rate outputs.

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Datasheet Details

Part number ODTSXN04
Manufacturer AMI
File Size 25.34 KB
Description CMOS Gate Array
Datasheet download datasheet ODTSXN04 Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2'76;1[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pulldown) and controlled slew rate outputs. Logic Symbol Truth Table ODTSXNxx A PADM A PADM LL HZ Z = High Impedance Pad Logic HDL Syntax Verilog .................... ODTSXNxx inst_name (PADM, A); VHDL...................... inst_name: ODTSXNxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF) ODTSXN04 8.1 4.90 ODTSXN08 8.1 4.90 Load ODTSXN12 8.1 4.90 ODTSXN16 8.1 4.90 ODTSXN24 8.1 4.90 Power Characteristics Cell Output Drive (mA) ODTSXN04 4 ODTSXN08 8 ODTSXN12 12 ODTSXN16 16 ODTSXN24 24 a. See page 2-15 for power equation.
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