Datasheet4U Logo Datasheet4U.com

ODTHXX24 - CMOS Gate Array

Description

ODTHXX24 is a high performance,24 mA, non-inverting, TTL-level output buffer piece.

📥 Download Datasheet

Datasheet Details

Part number ODTHXX24
Manufacturer AMI
File Size 17.43 KB
Description CMOS Gate Array
Datasheet download datasheet ODTHXX24 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer

Other Datasheets by AMI

Part Number Description
ODTHXE24 CMOS Gate Array
ODTSXE04 CMOS Gate Array
ODTSXE08 CMOS Gate Array
ODTSXE12 CMOS Gate Array
ODTSXE16 CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
2'7+;; ® $0,+*  PLFURQ &026 *DWH $UUD Description ODTHXX24 is a high performance,24 mA, non-inverting, TTL-level output buffer piece. Logic Symbol Truth Table Pin Loading ODTHXX24 A PADM A PADM LL HH Load A 14.5 eql HDL Syntax Verilog .................... ODTHXX24 inst_name (PADM, A); VHDL...................... inst_name: ODTHXX24 port map (PADM, A); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 249.7 Units nA Eq-load Output Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 15 A PADM tPLH tPHL 0.54 0.84 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 50 0.81 1.30 Capacitive Load (pF) 100 1.16 1.95 200 1.84 3.
Published: |