ODCXIP08
Description
ODCXIPxx is a family of 1 to 8 m A, inverting, CMOS-level, output buffer pieces with P-channel, open-drains (pull-up).
Logic Symbol
Truth Table
ODCXIPxx A
PADM
A PADM LH HZ Z = High Impedance
HDL Syntax Verilog ODCXIPxx inst_name (PADM, A); VHDL inst_name: ODCXIPxx port map (PADM, A);
Pin Loading
Pin Name A (eq-load) PADM (p F)
ODCXIP01 2.8 4.92
Load
ODCXIP02
ODCXIP04
2.8 2.8
4.92 4.92
ODCXIP08 3.9 4.93
Power Characteristics
Cell Output Drive (m A)
ODCXIP01
ODCXIP02
ODCXIP04
8 a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (n A)
EQLpd (Eq-load)
Pad Logic
4-21
2'&;,3[[
$0,+- PLFURQ &026
- DWH $UUD
Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
ODCXIP01
Capacitive Load (p F)
From: A To: PADM t ZH
15...
