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ODCSIP04 - CMOS Gate Array

General Description

ODCSIPxx is a family of 4 to 8 mA, inverting, CMOS-level output buffer pieces with P-channel open-drains (pull-up) and controlled slew rate outputs.

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Datasheet Details

Part number ODCSIP04
Manufacturer AMI
File Size 24.35 KB
Description CMOS Gate Array
Datasheet download datasheet ODCSIP04 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2'&6,3[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCSIPxx is a family of 4 to 8 mA, inverting, CMOS-level output buffer pieces with P-channel open-drains (pull-up) and controlled slew rate outputs. Logic Symbol Truth Table ODCSIPxx A SL PADM A PADM LH HZ Z = High Impedance HDL Syntax Verilog .................... ODCSIPxx inst_name (PADM, A); VHDL...................... inst_name: ODCSIPxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF) ODCSIP04 4.1 4.94 Power Characteristics Cell Output Drive (mA) ODCSIP04 4 ODCSIP08 8 ODCSIP12 12 a. See page 2-15 for power equation. Load ODCSIP08 4.1 4.94 ODCSIP12 4.1 4.94 Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 190.5 TBD 203.6 TBD 216.