JK124 - CMOS Gate Array

AMI

Download the JK124 datasheet PDF. This datasheet also covers the JK121 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

JK12x is a family of static, master-slave JK flip-flops.

SET and RESET are asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

JK124 cmos gate array by AMI - Datasheet Preview — Note: The manufacturer provides a single datasheet file (JK121-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	JK124
Manufacturer	AMI
File Size	48.38 KB
Description	CMOS Gate Array
Datasheet	JK124 Datasheet

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Other Datasheets by AMI

Part Number	Description
JK121	CMOS Gate Array
JK122	CMOS Gate Array
JK126	CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

-.[ ® $0,+* PLFURQ &026 *DWH $UUD Description JK12x is a family of static, master-slave JK flip-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol JK12x J SQ C K Q R Truth Table RN SN J K L L XX LHXX HLXX HHL L HH L H HHH L HHHH IL = Illegal C Q(n+1) QN(n+1) X IL IL XL H XH L ↑ NC NC ↑L H ↑H L ↑ QN(n) Q(n) NC = No Change Core Logic HDL Syntax Verilog .................... JK12x inst_name (Q, QN, C, J, K, RN, SN); VHDL...................... inst_name: JK12x port map (Q, QN, C, J, K, RN, SN); Pin Loading Pin Name J K C SN RN JK121 1.0 1.0 1.1 2.1 2.2 Equivalent Loads JK122 JK124 1.0 1.0 1.0 1.1 1.0 1.0 2.1 2.1 1.1 1.1 JK126 1.0 1.0 1.0 2.1 1.