| Description | ITEx is a family of two-phase inverting internal tristate buffers. Logic Symbol Truth Table ITEx A A EN QN E QN EN EN E A QN HLXZ LHLH L HH L L L X IL H H X IL IL = Illegal HDL Syntax Verilog .. ITEx inst_name (QN, A, E, EN); VHDL.... inst_name: ITEx port map (QN, A, E, EN); Pin Loading Pin Name A E EN QN ITE1 1.0 0.5 0.6 0.6 Equivalent Loads ITE2 ITE4 ... |
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| Datasheet |
 ITE6 Datasheet - 26.87KB |
