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Core Logic
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Description IIDx is a family of non-inverting clock drivers with a single output.
Logic Symbol
Truth Table
IIDx AQ
AQ
AQ LL HH
HDL Syntax Verilog .................... IIDx inst_name (Q, A); VHDL...................... inst_name: IIDx port map (Q, A);
Pin Loading Pin Name A
IID1 1.0
Equivalent Loads IID2 IID3 IID4 1.0 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
IID1 1.0 IID2 2.0
TBD TBD
2.3 3.8
IID3 3.0
TBD
5.5
IID4 3.0 IID6 4.0
TBD TBD
7.6 11.0
a. See page 2-15 for power equation.
IID6 2.1
3-124
®
®
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.
IID1 Datasheet
