DF124 Datasheet | AMI

')[ ® $0,+- PLFURQ &026 - DWH $UUD Description DF12x is a family of static, master-slave D flip-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF12x DSQ C Truth Table SN RN LL LH HL HH HH HH IL = Illegal D X X X L H X C Q QN X IL IL XHL XLH ↑LH ↑HL L NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF12x inst_name (Q, QN, C, D, RN, SN); VHDL...................... inst_name: DF12x port map (Q, QN, C, D, RN, SN); Pin Loading Pin Name D C SN RN DF121 1.0 1.0 2.1 2.2 Equivalent Loads DF122 1.0 1.0 1.0 1.0 2.1 2.1 2.2 1.0 DF126 1.0 1.0 2.1 1.0 Size...