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Core Logic
$1[
®
$0,+* PLFURQ &026 *DWH $UUD
Description AN1x is a family of AND-NOR circuits consisting of two 2-input AND gates into a 2-input NOR gate.
Logic Symbol
A B C D
Truth Table
A B CDQ
AN1x
L X L XH LXXLH
Q X L L XH
XLXLH
HHXX L
X XHH L
HDL Syntax Verilog .................... AN1x inst_name (Q, A, B, C, D); VHDL...................... inst_name: AN1x port map (Q, A, B, C, D);
Pin Loading
Pin Name
A B C D
AN11 1.0 1.0 1.0 1.0
Equivalent Loads
AN12
AN14
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
AN16 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
AN11
2.0
TBD
2.3
AN12
4.0
TBD
6.3
AN14
4.0
TBD
7.9
AN16
8.0
TBD
14.7
a. See page 2-15 for power equation.
AN11 Datasheet
